Fix dCmd sent while the execute stage is removed

Pass dhrystone benchmark without error !

src/main/scala/SpinalRiscv/Plugin/DBusSimplePlugin.scala

@@ -79,7 +79,7 @@ class DBusSimplePlugin extends Plugin[VexRiscv]{
       import execute._
 
       dCmd = master(Stream(DBusSimpleCmd())).setName("dCmd")
-      dCmd.valid := arbitration.isValid && input(MEMORY_ENABLE) && !arbitration.isStuckByOthers
+      dCmd.valid := arbitration.isValid && input(MEMORY_ENABLE) && !arbitration.isStuckByOthers && !arbitration.removeIt
       dCmd.wr := input(INSTRUCTION)(5)
       dCmd.address := input(SRC_ADD_SUB).asUInt
       dCmd.size := input(INSTRUCTION)(13 downto 12).asUInt

src/main/scala/SpinalRiscv/TopLevel.scala

@@ -41,7 +41,7 @@ object TopLevel {
 //        new LightShifterPlugin,
         new DBusSimplePlugin,
 //        new HazardSimplePlugin(false, true, false, true),
-        new HazardSimplePlugin(false, false, false, false),
+        new HazardSimplePlugin(true, true, true, true),
         new MulPlugin,
         new DivPlugin,
         new NoPredictionBranchPlugin(false)

src/test/cpp/testA/main.cpp

@@ -8,6 +8,10 @@
 #include <stdint.h>
 #include <cstring>
 #include <string.h>
+#include <iostream>
+#include <fstream>
+
+//#define REF
 
 class Memory{
 public:
@@ -21,7 +25,11 @@ public:
 	}
 
 	uint8_t* get(uint32_t address){
-		if(mem[address >> 20] == NULL) mem[address >> 20] = new uint8_t[1024*1024];
+		if(mem[address >> 20] == NULL) {
+			uint8_t* ptr = new uint8_t[1024*1024];
+			for(uint32_t i = 0;i < 1024*1024;i++) ptr[i] = 0xFF;
+			mem[address >> 20] = ptr;
+		}
 		return &mem[address >> 20][address & 0xFFFFF];
 	}
 
@@ -67,7 +75,7 @@ void loadHexImpl(string path,Memory* mem) {
 			uint32_t byteCount = hToI(line + 1, 2);
 			uint32_t nextAddr = hToI(line + 3, 4) + offset;
 			uint32_t key = hToI(line + 7, 2);
-			//printf("%d %d %d\n", byteCount, nextAddr,key);
+//			printf("%d %d %d\n", byteCount, nextAddr,key);
 			switch (key) {
 			case 0:
 				for (uint32_t i = 0; i < byteCount; i++) {
@@ -76,12 +84,16 @@ void loadHexImpl(string path,Memory* mem) {
 				}
 				break;
 			case 2:
+//				cout << offset << endl;
 				offset = hToI(line + 9, 4) << 4;
 				break;
 			case 4:
+//				cout << offset << endl;
 				offset = hToI(line + 9, 4) << 16;
 				break;
-
+			default:
+//				cout << "??? " << key << endl;
+				break;
 			}
 		}
 
@@ -111,7 +123,7 @@ class success : public std::exception { };
 
 uint32_t testsCounter = 0, successCounter = 0;
 
-double currentTime = 22;
+uint64_t currentTime = 22;
 double sc_time_stamp(){
 	return currentTime;
 }
@@ -125,10 +137,17 @@ public:
 	VVexRiscv* top;
 	int i;
 
+
+	ofstream regTraces;
+	ofstream memTraces;
+
+
 	Workspace(string name){
 		testsCounter++;
 		this->name = name;
 		top = new VVexRiscv;
+		regTraces.open (name + ".regTrace");
+		memTraces.open (name + ".memTrace");
 	}
 
 	virtual ~Workspace(){
@@ -172,7 +191,7 @@ public:
 		try {
 			// run simulation for 100 clock periods
 			for (i = 16; i < timeout*2; i+=2) {
-				currentTime = 55;
+				currentTime = i;
 				uint32_t iRsp_inst_next = top->iRsp_inst;
 				uint32_t dRsp_inst_next = VL_RANDOM_I(32);
 
@@ -193,20 +212,34 @@ public:
 
 					uint32_t addr = top->dCmd_payload_address;
 					if(top->dCmd_payload_wr){
+						memTraces << currentTime << " : WRITE mem" << (1 << top->dCmd_payload_size) << "[" << addr << "] = " << top->dCmd_payload_data << endl;
 						for(uint32_t b = 0;b < (1 << top->dCmd_payload_size);b++){
 							uint32_t offset = (addr+b)&0x3;
 							*mem.get(addr + b) = top->dCmd_payload_data >> (offset*8);
 						}
+
+						switch(addr){
+						case 0xF00FFF00u:
+							cout << mem[0xF00FFF00u];
+							break;
+						}
 					}else{
 						for(uint32_t b = 0;b < (1 << top->dCmd_payload_size);b++){
 							uint32_t offset = (addr+b)&0x3;
 							dRsp_inst_next &= ~(0xFF << (offset*8));
 							dRsp_inst_next |= mem[addr + b] << (offset*8);
 						}
+						switch(addr){
+						case 0xF00FFF10u:
+							dRsp_inst_next = i/2;
+							break;
+						}
+						memTraces << currentTime << " : READ  mem" << (1 << top->dCmd_payload_size) << "[" << addr << "] = " << dRsp_inst_next << endl;
+
 					}
 				}
 
-				checks();
+
 
 
 
@@ -217,8 +250,12 @@ public:
 
 					top->eval();
 					if(top->clk == 0){
-						top->iCmd_ready = VL_RANDOM_I(1);
-						top->dCmd_ready = VL_RANDOM_I(1);
+						top->iCmd_ready = VL_RANDOM_I(1) | 1;
+						top->dCmd_ready = VL_RANDOM_I(1) | 1;
+						if(top->VexRiscv->writeBack_RegFilePlugin_regFileWrite_valid == 1 && top->VexRiscv->writeBack_RegFilePlugin_regFileWrite_payload_address != 0){
+							regTraces << currentTime << " : reg[" << (uint32_t)top->VexRiscv->writeBack_RegFilePlugin_regFileWrite_payload_address << "] = " << top->VexRiscv->writeBack_RegFilePlugin_regFileWrite_payload_data << endl;
+						}
+						checks();
 					}
 				}
 				cycles += 1;
@@ -249,6 +286,7 @@ public:
 };
 uint32_t Workspace::cycles = 0;
 
+#ifndef REF
 #define testA1ReagFileWriteRef {1,10},{2,20},{3,40},{4,60}
 #define testA2ReagFileWriteRef {5,1},{7,3}
 uint32_t regFileWriteRefArray[][2] = {
@@ -308,6 +346,18 @@ public:
 		}
 	}
 };
+#endif
+class Dhrystone : public Workspace{
+public:
+
+	Dhrystone() : Workspace("Dhrystone") {
+		loadHex("../../resources/hex/dhrystoneO3M.hex");
+	}
+
+	virtual void checks(){
+
+	}
+};
 
 
 string riscvTestMain[] = {
@@ -390,7 +440,8 @@ int main(int argc, char **argv, char **env) {
 	printf("BOOT\n");
 	timespec startedAt = timer_start();
 
-	for(int idx = 0;idx < 2;idx++){
+	for(int idx = 0;idx < 1;idx++){
+		#ifndef  REF
 		TestA().run();
 		for(const string &name : riscvTestMain){
 			RiscvTest(name).run();
@@ -404,6 +455,8 @@ int main(int argc, char **argv, char **env) {
 		for(const string &name : riscvTestDiv){
 			RiscvTest(name).run();
 		}
+		#endif
+		Dhrystone().run(0.3e6);
 	}
 
 	uint64_t duration = timer_end(startedAt);

src/test/cpp/testA/refDiff.gtkw

@@ -0,0 +1,40 @@
+[*]
+[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI
+[*] Fri Mar 17 18:05:14 2017
+[*]
+[dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/testA/DhrystoneRef.vcd"
+[dumpfile_mtime] "Fri Mar 17 18:03:52 2017"
+[dumpfile_size] 1483111421
+[savefile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/testA/refDiff.gtkw"
+[timestart] 36700
+[size] 1774 451
+[pos] -775 -353
+*-2.000000 36713 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] TOP.
+[treeopen] TOP.VexRiscv.
+[sst_width] 201
+[signals_width] 583
+[sst_expanded] 1
+[sst_vpaned_height] 68
+@22
+TOP.VexRiscv.writeBack_RegFilePlugin_regFileWrite_payload_address[4:0]
+@24
+TOP.VexRiscv.writeBack_RegFilePlugin_regFileWrite_payload_data[31:0]
+@28
+TOP.VexRiscv.writeBack_RegFilePlugin_regFileWrite_valid
+TOP.VexRiscv.writeBack_arbitration_isValid
+TOP.VexRiscv.clk
+@22
+TOP.VexRiscv.core.writeBack_inInst_payload_instruction[31:0]
+TOP.VexRiscv.core.writeBack_inInst_payload_pcPlus4[31:0]
+TOP.dCmd_payload_address[31:0]
+TOP.dCmd_payload_data[31:0]
+@28
+TOP.dCmd_payload_size[1:0]
+TOP.dCmd_payload_wr
+TOP.dCmd_ready
+TOP.dCmd_valid
+@25
+TOP.dRsp_data[31:0]
+[pattern_trace] 1
+[pattern_trace] 0