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VexRiscv
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Clean and fix things to get all the non-linux configs and machine only configs working

This commit is contained in:
Charles Papon 2019-04-08 16:06:05 +02:00
parent 32921491b8
commit 21cb8615fd
14 changed files with 168 additions and 166 deletions
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4
src/main/scala/vexriscv/plugin/CsrPlugin.scala
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@ -380,7 +380,7 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
exceptionPending = False exceptionPending = False
timerInterrupt = in Bool() setName("timerInterrupt") timerInterrupt = in Bool() setName("timerInterrupt")
externalInterrupt = in Bool() setName("externalInterrupt") externalInterrupt = in Bool() setName("externalInterrupt")
softwareInterrupt = in Bool() setName("softwareInterrupt") softwareInterrupt = in Bool() setName("softwareInterrupt") default(False)
if(supervisorGen){ if(supervisorGen){
// timerInterruptS = in Bool() setName("timerInterruptS") // timerInterruptS = in Bool() setName("timerInterruptS")
externalInterruptS = in Bool() setName("externalInterruptS") externalInterruptS = in Bool() setName("externalInterruptS")
@ -714,7 +714,7 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
//Used to make the pipeline empty softly (for interrupts) //Used to make the pipeline empty softly (for interrupts)
val pipelineLiberator = new Area{ val pipelineLiberator = new Area{
when(interrupt){ when(interrupt){
decode.arbitration.haltByOther := True decode.arbitration.haltByOther := decode.arbitration.isValid
} }
val done = !stagesFromExecute.map(_.arbitration.isValid).orR && fetcher.pcValid(mepcCaptureStage) val done = !stagesFromExecute.map(_.arbitration.isValid).orR && fetcher.pcValid(mepcCaptureStage)

15
src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
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@ -217,14 +217,16 @@ class DBusCachedPlugin(config : DataCacheConfig,
cache.io.cpu.writeBack.address := U(input(REGFILE_WRITE_DATA)) cache.io.cpu.writeBack.address := U(input(REGFILE_WRITE_DATA))
if(withLrSc) cache.io.cpu.writeBack.clearAtomicEntries := service(classOf[IContextSwitching]).isContextSwitching if(withLrSc) cache.io.cpu.writeBack.clearAtomicEntries := service(classOf[IContextSwitching]).isContextSwitching
redoBranch.valid := False
redoBranch.payload := input(PC)
arbitration.flushAll setWhen(redoBranch.valid)
if(catchSomething) { if(catchSomething) {
exceptionBus.valid := False //cache.io.cpu.writeBack.mmuMiss || cache.io.cpu.writeBack.accessError || cache.io.cpu.writeBack.illegalAccess || cache.io.cpu.writeBack.unalignedAccess exceptionBus.valid := False //cache.io.cpu.writeBack.mmuMiss || cache.io.cpu.writeBack.accessError || cache.io.cpu.writeBack.illegalAccess || cache.io.cpu.writeBack.unalignedAccess
exceptionBus.badAddr := U(input(REGFILE_WRITE_DATA)) exceptionBus.badAddr := U(input(REGFILE_WRITE_DATA))
exceptionBus.code.assignDontCare() exceptionBus.code.assignDontCare()
}
redoBranch.valid := False
redoBranch.payload := input(PC)
arbitration.flushAll setWhen(redoBranch.valid)
when(arbitration.isValid && input(MEMORY_ENABLE)) { when(arbitration.isValid && input(MEMORY_ENABLE)) {
if (catchAccessError) when(cache.io.cpu.writeBack.accessError) { if (catchAccessError) when(cache.io.cpu.writeBack.accessError) {
@ -236,16 +238,17 @@ class DBusCachedPlugin(config : DataCacheConfig,
exceptionBus.valid := True exceptionBus.valid := True
exceptionBus.code := (input(MEMORY_WR) ? U(6) | U(4)).resized exceptionBus.code := (input(MEMORY_WR) ? U(6) | U(4)).resized
} }
when (cache.io.cpu.writeBack.mmuException) { if(catchIllegal) when (cache.io.cpu.writeBack.mmuException) {
exceptionBus.valid := True exceptionBus.valid := True
exceptionBus.code := (input(MEMORY_WR) ? U(15) | U(13)).resized exceptionBus.code := (input(MEMORY_WR) ? U(15) | U(13)).resized
} }
when(cache.io.cpu.redo) { when(cache.io.cpu.redo) {
redoBranch.valid := True redoBranch.valid := True
exceptionBus.valid := False if(catchSomething) exceptionBus.valid := False
}
} }
} }
arbitration.haltItself.setWhen(cache.io.cpu.writeBack.haltIt) arbitration.haltItself.setWhen(cache.io.cpu.writeBack.haltIt)
val rspShifted = Bits(32 bits) val rspShifted = Bits(32 bits)

1
src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala
View File

@ -253,6 +253,7 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
cache.io.cpu.fetch.mmuBus.rsp.isIoAccess := False cache.io.cpu.fetch.mmuBus.rsp.isIoAccess := False
cache.io.cpu.fetch.mmuBus.rsp.exception := False cache.io.cpu.fetch.mmuBus.rsp.exception := False
cache.io.cpu.fetch.mmuBus.rsp.refilling := False cache.io.cpu.fetch.mmuBus.rsp.refilling := False
cache.io.cpu.fetch.mmuBus.busy := False
} }
val flushStage = decode val flushStage = decode

1
src/main/scala/vexriscv/plugin/StaticMemoryTranslatorPlugin.scala
View File

@ -34,6 +34,7 @@ class StaticMemoryTranslatorPlugin(ioRange : UInt => Bool) extends Plugin[VexRis
port.bus.rsp.isIoAccess := ioRange(port.bus.rsp.physicalAddress) port.bus.rsp.isIoAccess := ioRange(port.bus.rsp.physicalAddress)
port.bus.rsp.exception := False port.bus.rsp.exception := False
port.bus.rsp.refilling := False port.bus.rsp.refilling := False
port.bus.busy := False
} }
} }
} }

117
src/test/cpp/raw/dcache/build/dcache.asm
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@ -6,74 +6,73 @@ Disassembly of section .crt_section:
80000000 <_start>: 80000000 <_start>:
80000000: 00000097 auipc ra,0x0 80000000: 00000097 auipc ra,0x0
80000004: 0b808093 addi ra,ra,184 # 800000b8 <fail> 80000004: 0b408093 addi ra,ra,180 # 800000b4 <fail>
80000008: 30509073 csrw mtvec,ra
8000000c <test1>: 80000008 <test1>:
8000000c: 00100e13 li t3,1 80000008: 00100e13 li t3,1
80000010: 00100093 li ra,1 8000000c: 00100093 li ra,1
80000014: 00300113 li sp,3 80000010: 00300113 li sp,3
80000018: 00208093 addi ra,ra,2 80000014: 00208093 addi ra,ra,2
8000001c: 08209e63 bne ra,sp,800000b8 <fail> 80000018: 08209e63 bne ra,sp,800000b4 <fail>
80000020 <test2>: 8000001c <test2>:
80000020: 00200e13 li t3,2 8000001c: 00200e13 li t3,2
80000024: f56700b7 lui ra,0xf5670 80000020: f56700b7 lui ra,0xf5670
80000028: 900ff137 lui sp,0x900ff 80000024: 900ff137 lui sp,0x900ff
8000002c: 40000313 li t1,1024 80000028: 40000313 li t1,1024
80000030 <test2_repeat>: 8000002c <test2_repeat>:
80000030: 00100193 li gp,1 8000002c: 00100193 li gp,1
80000034: 00200293 li t0,2 80000030: 00200293 li t0,2
80000038: 006303b3 add t2,t1,t1 80000034: 006303b3 add t2,t1,t1
8000003c: 007181b3 add gp,gp,t2 80000038: 007181b3 add gp,gp,t2
80000040: 007282b3 add t0,t0,t2 8000003c: 007282b3 add t0,t0,t2
80000044: 00312023 sw gp,0(sp) # 900ff000 <pass+0x100fef3c> 80000040: 00312023 sw gp,0(sp) # 900ff000 <pass+0x100fef40>
80000048: 0000a023 sw zero,0(ra) # f5670000 <pass+0x7566ff3c> 80000044: 0000a023 sw zero,0(ra) # f5670000 <pass+0x7566ff40>
8000004c: 00012203 lw tp,0(sp) 80000048: 00012203 lw tp,0(sp)
80000050: 06429463 bne t0,tp,800000b8 <fail> 8000004c: 06429463 bne t0,tp,800000b4 <fail>
80000054: ffc30313 addi t1,t1,-4 80000050: ffc30313 addi t1,t1,-4
80000058: 01008093 addi ra,ra,16 80000054: 01008093 addi ra,ra,16
8000005c: 01010113 addi sp,sp,16 80000058: 01010113 addi sp,sp,16
80000060: 0000500f 0x500f 8000005c: 0000500f 0x500f
80000064: fc0316e3 bnez t1,80000030 <test2_repeat> 80000060: fc0316e3 bnez t1,8000002c <test2_repeat>
80000068 <test3>: 80000064 <test3>:
80000068: 00300e13 li t3,3 80000064: 00300e13 li t3,3
8000006c: f56700b7 lui ra,0xf5670 80000068: f56700b7 lui ra,0xf5670
80000070: 900ff137 lui sp,0x900ff 8000006c: 900ff137 lui sp,0x900ff
80000074: 40000313 li t1,1024 80000070: 40000313 li t1,1024
80000078 <test3_repeat>: 80000074 <test3_repeat>:
80000078: 00200193 li gp,2 80000074: 00200193 li gp,2
8000007c: 00300293 li t0,3 80000078: 00300293 li t0,3
80000080: 006303b3 add t2,t1,t1 8000007c: 006303b3 add t2,t1,t1
80000084: 007181b3 add gp,gp,t2 80000080: 007181b3 add gp,gp,t2
80000088: 007282b3 add t0,t0,t2 80000084: 007282b3 add t0,t0,t2
8000008c: 00012203 lw tp,0(sp) # 900ff000 <pass+0x100fef3c> 80000088: 00012203 lw tp,0(sp) # 900ff000 <pass+0x100fef40>
80000090: 00312023 sw gp,0(sp) 8000008c: 00312023 sw gp,0(sp)
80000094: 0000a023 sw zero,0(ra) # f5670000 <pass+0x7566ff3c> 80000090: 0000a023 sw zero,0(ra) # f5670000 <pass+0x7566ff40>
80000098: 0000500f 0x500f 80000094: 0000500f 0x500f
8000009c: 00012203 lw tp,0(sp) 80000098: 00012203 lw tp,0(sp)
800000a0: 00429c63 bne t0,tp,800000b8 <fail> 8000009c: 00429c63 bne t0,tp,800000b4 <fail>
800000a4: ffc30313 addi t1,t1,-4 800000a0: ffc30313 addi t1,t1,-4
800000a8: 01008093 addi ra,ra,16 800000a4: 01008093 addi ra,ra,16
800000ac: 01010113 addi sp,sp,16 800000a8: 01010113 addi sp,sp,16
800000b0: fc0314e3 bnez t1,80000078 <test3_repeat> 800000ac: fc0314e3 bnez t1,80000074 <test3_repeat>
800000b4: 0100006f j 800000c4 <pass> 800000b0: 0100006f j 800000c0 <pass>
800000b8 <fail>: 800000b4 <fail>:
800000b8: f0100137 lui sp,0xf0100 800000b4: f0100137 lui sp,0xf0100
800000bc: f2410113 addi sp,sp,-220 # f00fff24 <pass+0x700ffe60> 800000b8: f2410113 addi sp,sp,-220 # f00fff24 <pass+0x700ffe64>
800000c0: 01c12023 sw t3,0(sp) 800000bc: 01c12023 sw t3,0(sp)
800000c4 <pass>: 800000c0 <pass>:
800000c4: f0100137 lui sp,0xf0100 800000c0: f0100137 lui sp,0xf0100
800000c8: f2010113 addi sp,sp,-224 # f00fff20 <pass+0x700ffe5c> 800000c4: f2010113 addi sp,sp,-224 # f00fff20 <pass+0x700ffe60>
800000cc: 00012023 sw zero,0(sp) 800000c8: 00012023 sw zero,0(sp)
800000cc: 00000013 nop
800000d0: 00000013 nop 800000d0: 00000013 nop
800000d4: 00000013 nop 800000d4: 00000013 nop
800000d8: 00000013 nop 800000d8: 00000013 nop
800000dc: 00000013 nop 800000dc: 00000013 nop
800000e0: 00000013 nop 800000e0: 00000013 nop
800000e4: 00000013 nop

28
src/test/cpp/raw/dcache/build/dcache.hex
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@ -1,17 +1,17 @@
:0200000480007A :0200000480007A
:10000000970000009380800B73905030130E100007 :10000000970000009380400B130E10009300100027
:10001000930010001301300093802000639E20089D :100010001301300093802000639E2008130E2000FF
:10002000130E2000B70067F537F10F90130300405F :10002000B70067F537F10F901303004093011000FC
:100030009301100093022000B3036300B3817100A9 :1000300093022000B3036300B3817100B3827200A6
:10004000B38272002320310023A0000003220100AC :100040002320310023A00000032201006394420614
:10005000639442061303C3FF93800001130101015F :100050001303C3FF93800001130101010F5000003F
:100060000F500000E31603FC130E3000B70067F5D5 :10006000E31603FC130E3000B70067F537F10F906D
:1000700037F10F90130300409301200093023000EA :10007000130300409301200093023000B303630098
:10008000B3036300B3817100B382720003220100E5 :10008000B3817100B382720003220100232031008A
:100090002320310023A000000F50000003220100A4 :1000900023A000000F50000003220100639C4200D7
:1000A000639C42001303C3FF93800001130101010D :1000A0001303C3FF9380000113010101E31403FC58
:1000B000E31403FC6F000001370110F0130141F25B :1000B0006F000001370110F0130141F22320C1014C
:1000C0002320C101370110F0130101F223200100A8 :1000C000370110F0130101F223200100130000009A
:1000D00013000000130000001300000013000000D4 :1000D00013000000130000001300000013000000D4
:0800E0001300000013000000F2 :0400E0001300000009
:00000001FF :00000001FF

2
src/test/cpp/raw/dcache/src/crt.S
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@ -3,7 +3,7 @@
_start: _start:
la x1, fail la x1, fail
csrw mtvec, x1 //csrw mtvec, x1
test1: //Dummy test test1: //Dummy test
li TEST_ID, 1 li TEST_ID, 1

69
src/test/cpp/raw/icache/build/icache.asm
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@ -6,48 +6,43 @@ Disassembly of section .crt_section:
80000000 <_start>: 80000000 <_start>:
80000000: 00000097 auipc ra,0x0 80000000: 00000097 auipc ra,0x0
80000004: 05408093 addi ra,ra,84 # 80000054 <fail> 80000004: 04408093 addi ra,ra,68 # 80000044 <fail>
80000008: 30509073 csrw mtvec,ra
8000000c <test1>: 80000008 <test1>:
8000000c: 00100e13 li t3,1 80000008: 00100e13 li t3,1
80000010: 00100093 li ra,1 8000000c: 00100093 li ra,1
80000014: 00300113 li sp,3 80000010: 00300113 li sp,3
80000018: 00208093 addi ra,ra,2 80000014: 00208093 addi ra,ra,2
8000001c: 02209c63 bne ra,sp,80000054 <fail> 80000018: 02209663 bne ra,sp,80000044 <fail>
80000020 <test2>: 8000001c <test2>:
80000020: 00200e13 li t3,2 8000001c: 00200e13 li t3,2
80000024: 01300093 li ra,19 80000020: 01300093 li ra,19
80000028: 00000117 auipc sp,0x0 80000024: 00000117 auipc sp,0x0
8000002c: 02410113 addi sp,sp,36 # 8000004c <test2_trigger> 80000028: 01810113 addi sp,sp,24 # 8000003c <test2_trigger>
80000030: 0100006f j 80000040 <test2_aligned> 8000002c: 0040006f j 80000030 <test2_aligned>
80000034: 00000013 nop
80000038: 00000013 nop
8000003c: 00000013 nop
80000040 <test2_aligned>: 80000030 <test2_aligned>:
80000040: 00112023 sw ra,0(sp) 80000030: 00112023 sw ra,0(sp)
80000044: 0000100f fence.i 80000034: 0000100f fence.i
80000048: 0040006f j 8000004c <test2_trigger> 80000038: 0040006f j 8000003c <test2_trigger>
8000004c <test2_trigger>: 8000003c <test2_trigger>:
8000004c: 0080006f j 80000054 <fail> 8000003c: 0080006f j 80000044 <fail>
80000050: 0100006f j 80000060 <pass> 80000040: 0100006f j 80000050 <pass>
80000054 <fail>: 80000044 <fail>:
80000054: f0100137 lui sp,0xf0100 80000044: f0100137 lui sp,0xf0100
80000058: f2410113 addi sp,sp,-220 # f00fff24 <pass+0x700ffec4> 80000048: f2410113 addi sp,sp,-220 # f00fff24 <pass+0x700ffed4>
8000005c: 01c12023 sw t3,0(sp) 8000004c: 01c12023 sw t3,0(sp)
80000060 <pass>: 80000050 <pass>:
80000060: f0100137 lui sp,0xf0100 80000050: f0100137 lui sp,0xf0100
80000064: f2010113 addi sp,sp,-224 # f00fff20 <pass+0x700ffec0> 80000054: f2010113 addi sp,sp,-224 # f00fff20 <pass+0x700ffed0>
80000068: 00012023 sw zero,0(sp) 80000058: 00012023 sw zero,0(sp)
8000005c: 00000013 nop
80000060: 00000013 nop
80000064: 00000013 nop
80000068: 00000013 nop
8000006c: 00000013 nop 8000006c: 00000013 nop
80000070: 00000013 nop 80000070: 00000013 nop
80000074: 00000013 nop
80000078: 00000013 nop
8000007c: 00000013 nop
80000080: 00000013 nop
...

17
src/test/cpp/raw/icache/build/icache.hex
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@ -1,11 +1,10 @@
:0200000480007A :0200000480007A
:10000000970000009380400573905030130E10004D :100000009700000093804004130E1000930010002E
:10001000930010001301300093802000639C2002A5 :10001000130130009380200063962002130E20000D
:10002000130E20009300300117010000130141025C :100020009300300117010000130181016F004000AF
:100030006F00000113000000130000001300000017 :10003000232011000F1000006F0040006F008000AF
:10004000232011000F1000006F0040006F0080009F :100040006F000001370110F0130141F22320C101BC
:100050006F000001370110F0130141F22320C101AC :10005000370110F0130101F223200100130000000A
:10006000370110F0130101F22320010013000000FA :100060001300000013000000130000001300000044
:100070001300000013000000130000001300000034 :040070001300000079
:10008000130000000000000000000000000000005D
:00000001FF :00000001FF

2
src/test/cpp/raw/icache/src/crt.S
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@ -3,7 +3,7 @@
_start: _start:
la x1, fail la x1, fail
csrw mtvec, x1 // csrw mtvec, x1
test1: //Dummy test test1: //Dummy test
li TEST_ID, 1 li TEST_ID, 1

39
src/test/cpp/raw/machineCsr/build/machineCsr.asm
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@ -29,26 +29,26 @@ Disassembly of section .crt_section:
80000044: 01de7f33 and t5,t3,t4 80000044: 01de7f33 and t5,t3,t4
80000048: 000f1863 bnez t5,80000058 <mepcFixed> 80000048: 000f1863 bnez t5,80000058 <mepcFixed>
8000004c: 34102ef3 csrr t4,mepc 8000004c: 34102ef3 csrr t4,mepc
80000050: 004e8e93 addi t4,t4,4 # 80000004 <_start+0xffffff70> 80000050: 004e8e93 addi t4,t4,4 # 80000004 <unalignedPcA+0xfffffe60>
80000054: 341e9073 csrw mepc,t4 80000054: 341e9073 csrw mepc,t4
80000058 <mepcFixed>: 80000058 <mepcFixed>:
80000058: 80000eb7 lui t4,0x80000 80000058: 80000eb7 lui t4,0x80000
8000005c: 003e8e93 addi t4,t4,3 # 80000003 <_start+0xffffff6f> 8000005c: 003e8e93 addi t4,t4,3 # 80000003 <unalignedPcA+0xfffffe5f>
80000060: 01ce9863 bne t4,t3,80000070 <noSoftwareInterrupt> 80000060: 01ce9863 bne t4,t3,80000070 <noSoftwareInterrupt>
80000064: f0013c37 lui s8,0xf0013 80000064: f0013c37 lui s8,0xf0013
80000068: 00000c93 li s9,0 80000068: 00000c93 li s9,0
8000006c: 019c2023 sw s9,0(s8) # f0013000 <_start+0x70012f6c> 8000006c: 019c2023 sw s9,0(s8) # f0013000 <unalignedPcA+0x70012e5c>
80000070 <noSoftwareInterrupt>: 80000070 <noSoftwareInterrupt>:
80000070: 80000eb7 lui t4,0x80000 80000070: 80000eb7 lui t4,0x80000
80000074: 007e8e93 addi t4,t4,7 # 80000007 <_start+0xffffff73> 80000074: 007e8e93 addi t4,t4,7 # 80000007 <unalignedPcA+0xfffffe63>
80000078: 01ce9463 bne t4,t3,80000080 <noTimerInterrupt> 80000078: 01ce9463 bne t4,t3,80000080 <noTimerInterrupt>
8000007c: 30405073 csrwi mie,0 8000007c: 30405073 csrwi mie,0
80000080 <noTimerInterrupt>: 80000080 <noTimerInterrupt>:
80000080: 80000eb7 lui t4,0x80000 80000080: 80000eb7 lui t4,0x80000
80000084: 00be8e93 addi t4,t4,11 # 8000000b <_start+0xffffff77> 80000084: 00be8e93 addi t4,t4,11 # 8000000b <unalignedPcA+0xfffffe67>
80000088: 01ce9463 bne t4,t3,80000090 <noExernalInterrupt> 80000088: 01ce9463 bne t4,t3,80000090 <noExernalInterrupt>
8000008c: 30405073 csrwi mie,0 8000008c: 30405073 csrwi mie,0
@ -65,7 +65,7 @@ Disassembly of section .crt_section:
800000ac: 30429073 csrw mie,t0 800000ac: 30429073 csrw mie,t0
800000b0: f0013c37 lui s8,0xf0013 800000b0: f0013c37 lui s8,0xf0013
800000b4: 00100c93 li s9,1 800000b4: 00100c93 li s9,1
800000b8: 019c2023 sw s9,0(s8) # f0013000 <_start+0x70012f6c> 800000b8: 019c2023 sw s9,0(s8) # f0013000 <unalignedPcA+0x70012e5c>
800000bc: 00000013 nop 800000bc: 00000013 nop
800000c0: 00000013 nop 800000c0: 00000013 nop
800000c4: 00000013 nop 800000c4: 00000013 nop
@ -101,7 +101,7 @@ Disassembly of section .crt_section:
8000013c: 00000013 nop 8000013c: 00000013 nop
80000140: 00500e13 li t3,5 80000140: 00500e13 li t3,5
80000144: f01001b7 lui gp,0xf0100 80000144: f01001b7 lui gp,0xf0100
80000148: f4018193 addi gp,gp,-192 # f00fff40 <_start+0x700ffeac> 80000148: f4018193 addi gp,gp,-192 # f00fff40 <unalignedPcA+0x700ffd9c>
8000014c: 0001a203 lw tp,0(gp) 8000014c: 0001a203 lw tp,0(gp)
80000150: 0041a283 lw t0,4(gp) 80000150: 0041a283 lw t0,4(gp)
80000154: 3ff20213 addi tp,tp,1023 # 3ff <trap_entry-0x7ffffc21> 80000154: 3ff20213 addi tp,tp,1023 # 3ff <trap_entry-0x7ffffc21>
@ -124,15 +124,18 @@ Disassembly of section .crt_section:
80000198: 00c00e13 li t3,12 80000198: 00c00e13 li t3,12
8000019c: 00d00e13 li t3,13 8000019c: 00d00e13 li t3,13
800001a0: 00002083 lw ra,0(zero) # 0 <trap_entry-0x80000020> 800001a0: 00002083 lw ra,0(zero) # 0 <trap_entry-0x80000020>
800001a4: 00002083 lw ra,0(zero) # 0 <trap_entry-0x80000020>
800001a8: 00e00e13 li t3,14 800001a4 <unalignedPcA>:
800001ac: 20200073 hret 800001a4: 0020006f j 800001a6 <unalignedPcA+0x2>
800001b0: 00f00e13 li t3,15 800001a8: 00002083 lw ra,0(zero) # 0 <trap_entry-0x80000020>
800001b4: f01000b7 lui ra,0xf0100 800001ac: 00e00e13 li t3,14
800001b8: f6008093 addi ra,ra,-160 # f00fff60 <_start+0x700ffecc> 800001b0: 20200073 hret
800001bc: 0000a103 lw sp,0(ra) 800001b4: 00f00e13 li t3,15
800001c0: 01000e13 li t3,16 800001b8: f01000b7 lui ra,0xf0100
800001c4: 0020a023 sw sp,0(ra) 800001bc: f6008093 addi ra,ra,-160 # f00fff60 <unalignedPcA+0x700ffdbc>
800001c8: 01100e13 li t3,17 800001c0: 0000a103 lw sp,0(ra)
800001cc: 00008067 ret 800001c4: 01000e13 li t3,16
800001c8: 0020a023 sw sp,0(ra)
800001cc: 01100e13 li t3,17
800001d0: 00008067 ret
... ...

8
src/test/cpp/raw/machineCsr/build/machineCsr.hex
View File

@ -25,9 +25,9 @@
:1001700073005010130E80009301100023A0410063 :1001700073005010130E80009301100023A0410063
:10018000130E900023904100130EA00003A2010063 :10018000130E900023904100130EA00003A2010063
:10019000130EB00003920100130EC000130ED00026 :10019000130EB00003920100130EC000130ED00026
:1001A0008320000083200000130EE0007300202055 :1001A000832000006F00200083200000130EE00079
:1001B000130EF000B70010F0938000F603A10000CA :1001B00073002020130EF000B70010F0938000F6BB
:1001C000130E000123A02000130E10016780000011 :1001C00003A10000130E000123A02000130E100154
:1001D000000000000000000000000000000000001F :1001D0006780000000000000000000000000000038
:0400000580000094E3 :0400000580000094E3
:00000001FF :00000001FF

1
src/test/cpp/raw/machineCsr/makefile
View File

@ -1,5 +1,6 @@
ifeq ($(COMPRESSED),yes) ifeq ($(COMPRESSED),yes)
PROJ_NAME=machineCsrCompressed PROJ_NAME=machineCsrCompressed
CFLAGS=-DCOMPRESSED
else else
PROJ_NAME=machineCsr PROJ_NAME=machineCsr
endif endif

2
src/test/cpp/raw/machineCsr/src/crt.S
View File

@ -124,7 +124,7 @@ _start:
li x28, 13 li x28, 13
lw x1,0(x0) lw x1,0(x0)
#ifdef COMPRESSED #ifndef COMPRESSED
unalignedPcA: unalignedPcA:
j unalignedPcA+2 j unalignedPcA+2
#endif #endif