Merge pull request #171 from tcal-x/cfu-spec
CFU spec -- update immed data sent in place of RS2.
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21d24eb07f
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@ -16,6 +16,7 @@ object Riscv{
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case class IMM(instruction : Bits) extends Area{
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// immediates
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def i = instruction(31 downto 20)
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def h = instruction(31 downto 24)
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def s = instruction(31 downto 25) ## instruction(11 downto 7)
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def b = instruction(31) ## instruction(7) ## instruction(30 downto 25) ## instruction(11 downto 8)
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def u = instruction(31 downto 12) ## U"x000"
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@ -24,6 +25,7 @@ object Riscv{
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// sign-extend immediates
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def i_sext = B((19 downto 0) -> i(11)) ## i
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def h_sext = B((23 downto 0) -> h(7)) ## h
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def s_sext = B((19 downto 0) -> s(11)) ## s
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def b_sext = B((18 downto 0) -> b(11)) ## b ## False
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def j_sext = B((10 downto 0) -> j(19)) ## j ## False
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@ -114,7 +114,7 @@ class CfuPlugin(val stageCount : Int,
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val CFU_ENABLE = new Stageable(Bool()).setCompositeName(this, "CFU_ENABLE")
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val CFU_IN_FLIGHT = new Stageable(Bool()).setCompositeName(this, "CFU_IN_FLIGHT")
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val CFU_ENCODING = new Stageable(UInt(log2Up(encodings.size) bits)).setCompositeName(this, "CFU_ENCODING")
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val CFU_INPUT_2_KIND = new Stageable(CfuPlugin.Input2Kind()).setCompositeName(this, "CFU_ENCODING")
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val CFU_INPUT_2_KIND = new Stageable(CfuPlugin.Input2Kind()).setCompositeName(this, "CFU_INPUT_2_KIND")
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override def setup(pipeline: VexRiscv): Unit = {
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import pipeline._
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@ -187,7 +187,7 @@ class CfuPlugin(val stageCount : Int,
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if(p.CFU_INPUTS >= 1) bus.cmd.inputs(0) := input(RS1)
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if(p.CFU_INPUTS >= 2) bus.cmd.inputs(1) := input(CFU_INPUT_2_KIND).mux(
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CfuPlugin.Input2Kind.RS -> input(RS2),
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CfuPlugin.Input2Kind.IMM_I -> IMM(input(INSTRUCTION)).i_sext
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CfuPlugin.Input2Kind.IMM_I -> IMM(input(INSTRUCTION)).h_sext
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)
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}
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