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Fix d$ invalidation when the mmu is enabled

This commit is contained in:
Dolu1990 2023-02-22 13:15:57 +01:00
parent 15a665af53
commit 220b599c9a
1 changed files with 11 additions and 9 deletions
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20
src/main/scala/vexriscv/ip/DataCache.scala
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@ -1063,16 +1063,18 @@ class DataCache(val p : DataCacheConfig, mmuParameter : MemoryTranslatorBusParam
}
//remove side effects on exceptions
when(consistancyHazard || mmuRsp.refilling || io.cpu.writeBack.accessError || io.cpu.writeBack.mmuException || io.cpu.writeBack.unalignedAccess){
io.mem.cmd.valid := False
tagsWriteCmd.valid := False
dataWriteCmd.valid := False
loaderValid := False
io.cpu.writeBack.haltIt := False
if(withInternalLrSc) lrSc.reserved := lrSc.reserved
if(withExternalAmo) amo.external.state := LR_CMD
when(io.cpu.writeBack.isValid) {
when(consistancyHazard || mmuRsp.refilling || io.cpu.writeBack.accessError || io.cpu.writeBack.mmuException || io.cpu.writeBack.unalignedAccess) {
io.mem.cmd.valid := False
tagsWriteCmd.valid := False
dataWriteCmd.valid := False
loaderValid := False
io.cpu.writeBack.haltIt := False
if (withInternalLrSc) lrSc.reserved := lrSc.reserved
if (withExternalAmo) amo.external.state := LR_CMD
}
io.cpu.redo setWhen((mmuRsp.refilling || consistancyHazard))
}
io.cpu.redo setWhen(io.cpu.writeBack.isValid && (mmuRsp.refilling || consistancyHazard))
assert(!(io.cpu.writeBack.isValid && !io.cpu.writeBack.haltIt && io.cpu.writeBack.isStuck), "writeBack stuck by another plugin is not allowed", ERROR)
}