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All tests passing on new PMP plugin

This commit is contained in:
Samuel Lindemer 2021-05-28 13:54:55 +02:00
parent 4a2dc0ff5f
commit 24a534acff
9 changed files with 379 additions and 461 deletions
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2
src/main/scala/vexriscv/demo/GenSecure.scala
View File

@ -41,7 +41,7 @@ object GenSecure extends App {
),
new PmpPlugin(
regions = 16,
granularity = 256,
granularity = 32,
ioRange = _(31 downto 28) === 0xf
),
new DecoderSimplePlugin(

8
src/main/scala/vexriscv/plugin/CsrPlugin.scala
View File

@ -366,6 +366,8 @@ case class CsrMapping() extends Area with CsrInterface {
override def duringAny(): Bool = ???
override def duringAnyRead(body: => Unit) : Unit = always += CsrDuringRead(() => body)
override def duringAnyWrite(body: => Unit) : Unit = always += CsrDuringWrite(() => body)
override def onAnyRead(body: => Unit) : Unit = always += CsrOnRead(() => body)
override def onAnyWrite(body: => Unit) : Unit = always += CsrOnWrite(() => body)
override def readData() = readDataSignal
override def writeData() = writeDataSignal
override def allowCsr() = allowCsrSignal := True
@ -388,6 +390,8 @@ trait CsrInterface{
}
def duringAnyRead(body: => Unit) : Unit //Called all the durration of a Csr write instruction in the execute stage
def duringAnyWrite(body: => Unit) : Unit //same than above for read
def onAnyRead(body: => Unit) : Unit
def onAnyWrite(body: => Unit) : Unit
def allowCsr() : Unit //In case your csr do not use the regular API with csrAddress but is implemented using "side channels", you can call that if the current csr is implemented
def isHazardFree() : Bool // You should not have any side effect nor use readData() until this return True
@ -517,6 +521,8 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
override def duringAny(): Bool = pipeline.execute.arbitration.isValid && pipeline.execute.input(IS_CSR)
override def duringAnyRead(body: => Unit) = csrMapping.duringAnyRead(body)
override def duringAnyWrite(body: => Unit) = csrMapping.duringAnyWrite(body)
override def onAnyRead(body: => Unit) = csrMapping.onAnyRead(body)
override def onAnyWrite(body: => Unit) = csrMapping.onAnyWrite(body)
override def allowCsr() = csrMapping.allowCsr()
override def readData() = csrMapping.readData()
override def writeData() = csrMapping.writeData()
@ -1264,6 +1270,8 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
csrMapping.always.foreach {
case element : CsrDuringWrite => when(writeInstruction){element.doThat()}
case element : CsrDuringRead => when(readInstruction){element.doThat()}
case element : CsrOnWrite => when(writeEnable){element.doThat()}
case element : CsrOnRead => when(readEnable){element.doThat()}
}
illegalAccess clearWhen(csrMapping.allowCsrSignal)

159
src/main/scala/vexriscv/plugin/PmpPlugin.scala
View File

@ -62,6 +62,10 @@ import spinal.lib.fsm._
*
* NA4: This is essentially an edge case of NAPOT where the entire pmpaddr#
* register defines a 4-byte wide region.
*
* N.B. THIS IMPLEMENTATION ONLY SUPPORTS NAPOT ADDRESSING. REGIONS ARE NOT
* ORDERED BY PRIORITY. A PERMISSION IS GRANTED TO AN ACCESS IF ANY MATCHING
* PMP REGION HAS THAT PERMISSION ENABLED.
*/
trait Pmp {
@ -124,114 +128,74 @@ class PmpPlugin(regions : Int, granularity : Int, ioRange : UInt => Bool) extend
val pmpcfg = Vector.fill(regions)(Reg(Bits(8 bits)) init(0))
val base, mask = Vector.fill(regions)(Reg(UInt(xlen - cutoff bits)))
// object PMPCFG extends Stageable(Bool)
// object PMPADDR extends Stageable(Bool)
// decode plug new Area {
// import decode._
// insert(PMPCFG) := input(INSTRUCTION)(31 downto 24) === 0x3a
// insert(PMPADDR) := input(INSTRUCTION)(31 downto 24) === 0x3b
// }
def machineMode : Bool = privilegeService.isMachine()
execute plug new Area {
import execute._
val mask0 = mask(U"4'x0")
val mask1 = mask(U"4'x1")
val mask2 = mask(U"4'x2")
val mask3 = mask(U"4'x3")
val mask4 = mask(U"4'x4")
val mask5 = mask(U"4'x5")
val mask6 = mask(U"4'x6")
val mask7 = mask(U"4'x7")
val mask8 = mask(U"4'x8")
val mask9 = mask(U"4'x9")
val mask10 = mask(U"4'xa")
val mask11 = mask(U"4'xb")
val mask12 = mask(U"4'xc")
val mask13 = mask(U"4'xd")
val mask14 = mask(U"4'xe")
val mask15 = mask(U"4'xf")
val base0 = base(U"4'x0")
val base1 = base(U"4'x1")
val base2 = base(U"4'x2")
val base3 = base(U"4'x3")
val base4 = base(U"4'x4")
val base5 = base(U"4'x5")
val base6 = base(U"4'x6")
val base7 = base(U"4'x7")
val base8 = base(U"4'x8")
val base9 = base(U"4'x9")
val base10 = base(U"4'xa")
val base11 = base(U"4'xb")
val base12 = base(U"4'xc")
val base13 = base(U"4'xd")
val base14 = base(U"4'xe")
val base15 = base(U"4'xf")
val pmpcfg0 = pmpcfg(0)
val pmpcfg1 = pmpcfg(1)
val pmpcfg2 = pmpcfg(2)
val pmpcfg3 = pmpcfg(3)
val pmpcfg4 = pmpcfg(4)
val pmpcfg5 = pmpcfg(5)
val pmpcfg6 = pmpcfg(6)
val pmpcfg7 = pmpcfg(7)
val pmpcfg8 = pmpcfg(8)
val pmpcfg9 = pmpcfg(9)
val pmpcfg10 = pmpcfg(10)
val pmpcfg11 = pmpcfg(11)
val pmpcfg12 = pmpcfg(12)
val pmpcfg13 = pmpcfg(13)
val pmpcfg14 = pmpcfg(14)
val pmpcfg15 = pmpcfg(15)
val csrAddress = input(INSTRUCTION)(csrRange)
val pmpIndex = csrAddress(log2Up(regions) - 1 downto 0).asUInt
val pmpIndexReg = Reg(UInt(log2Up(regions) bits))
val pmpSelect = pmpIndex(log2Up(regions) - 3 downto 0)
val pmpSelectReg = Reg(UInt(log2Up(regions) - 2 bits))
val pmpAccessCfg = RegInit(False)
val pmpAccessAddr = RegInit(False)
val writeData = Reg(Bits(xlen bits))
val pending = RegInit(False)
val hazardFree = csrService.isHazardFree()
def reconfigure() = {
pending := True
writeData := csrService.writeData()
pmpIndexReg := pmpIndex
pmpSelectReg := pmpSelect
pmpAccessCfg := input(INSTRUCTION)(31 downto 24) === 0x3a
pmpAccessAddr := input(INSTRUCTION)(31 downto 24) === 0x3b
val csrAddress = input(INSTRUCTION)(csrRange)
val pmpNcfg = csrAddress(log2Up(regions) - 1 downto 0).asUInt
val pmpcfgN = pmpNcfg(log2Up(regions) - 3 downto 0)
val pmpcfgCsr = input(INSTRUCTION)(31 downto 24) === 0x3a
val pmpaddrCsr = input(INSTRUCTION)(31 downto 24) === 0x3b
val pmpNcfg_ = Reg(UInt(log2Up(regions) bits))
val pmpcfgN_ = Reg(UInt(log2Up(regions) - 2 bits))
val pmpcfgCsr_ = RegInit(False)
val pmpaddrCsr_ = RegInit(False)
val writeData_ = Reg(Bits(xlen bits))
csrService.duringAnyRead {
when (machineMode) {
when (pmpcfgCsr) {
csrService.allowCsr()
csrService.readData() :=
pmpcfg(pmpcfgN @@ U(3, 2 bits)) ##
pmpcfg(pmpcfgN @@ U(2, 2 bits)) ##
pmpcfg(pmpcfgN @@ U(1, 2 bits)) ##
pmpcfg(pmpcfgN @@ U(0, 2 bits))
}
when (pmpaddrCsr) {
csrService.allowCsr()
csrService.readData() := pmpaddr.readAsync(pmpNcfg).asBits
}
}
}
for (i <- 0 until regions) {
csrService.onRead(0x3b0 + i) {
csrService.readData() := pmpaddr.readAsync(pmpIndex).asBits
csrService.duringAnyWrite {
when ((pmpcfgCsr | pmpaddrCsr) & machineMode) {
csrService.allowCsr()
}
csrService.onWrite(0x3b0 + i) { reconfigure() }
}
for (i <- 0 until (regions / 4)) {
csrService.onRead(0x3a0 + i) {
csrService.readData() := pmpcfg(i * 4 + 3) ## pmpcfg(i * 4 + 2) ## pmpcfg(i * 4 + 1) ## pmpcfg(i * 4)
csrService.onAnyWrite {
when ((pmpcfgCsr | pmpaddrCsr) & machineMode) {
pending := True
writeData_ := csrService.writeData()
pmpNcfg_ := pmpNcfg
pmpcfgN_ := pmpcfgN
pmpaddrCsr_ := pmpcfgCsr
pmpcfgCsr_ := pmpaddrCsr
}
csrService.onWrite(0x3a0 + i) { reconfigure() }
}
val writer = new Area {
when (pending) {
arbitration.haltItself := True
when (hazardFree & pmpAccessCfg) {
val overwrite = writeData.subdivideIn(8 bits)
when (hazardFree & pmpaddrCsr_) {
val overwrite = writeData_.subdivideIn(8 bits)
for (i <- 0 until 4) {
when (~pmpcfg(pmpSelectReg @@ U(i, 2 bits))(lBit)) {
pmpcfg(pmpSelectReg @@ U(i, 2 bits)).assignFromBits(overwrite(i))
when (~pmpcfg(pmpcfgN_ @@ U(i, 2 bits))(lBit)) {
pmpcfg(pmpcfgN_ @@ U(i, 2 bits)).assignFromBits(overwrite(i))
}
}
}
}
val locked = pmpcfg(pmpIndex)(lBit)
pmpaddr.write(pmpIndex, writeData.asUInt, ~locked & pmpAccessAddr & pending & hazardFree)
val locked = pmpcfg(pmpNcfg_)(lBit)
pmpaddr.write(pmpNcfg_, writeData_.asUInt, ~locked & pmpcfgCsr_ & pending & hazardFree)
}
val controller = new StateMachine {
@ -250,9 +214,9 @@ class PmpPlugin(regions : Int, granularity : Int, ioRange : UInt => Bool) extend
}
whenIsActive {
when (pending & hazardFree) {
when (pmpAccessCfg) {
when (pmpaddrCsr_) {
goto(stateCfg)
}.elsewhen (pmpAccessAddr) {
}.elsewhen (pmpcfgCsr_) {
goto(stateAddr)
}
}
@ -260,7 +224,7 @@ class PmpPlugin(regions : Int, granularity : Int, ioRange : UInt => Bool) extend
}
val stateCfg : State = new State {
onEntry (counter := pmpSelectReg @@ U(0, 2 bits))
onEntry (counter := pmpcfgN_ @@ U(0, 2 bits))
whenIsActive {
counter := counter + 1
when (counter(1 downto 0) === 3) {
@ -272,12 +236,12 @@ class PmpPlugin(regions : Int, granularity : Int, ioRange : UInt => Bool) extend
}
val stateAddr : State = new State {
onEntry (counter := pmpIndexReg)
onEntry (counter := pmpNcfg_)
whenIsActive (goto(stateIdle))
}
when (pmpAccessAddr) {
setter.io.addr := writeData.asUInt
when (pmpcfgCsr_) {
setter.io.addr := writeData_.asUInt
} otherwise {
setter.io.addr := pmpaddr.readAsync(counter)
}
@ -290,11 +254,10 @@ class PmpPlugin(regions : Int, granularity : Int, ioRange : UInt => Bool) extend
}
pipeline plug new Area {
def getHits(address : UInt) = {
(0 until regions).map(i =>
((address & mask(U(i, log2Up(regions) bits))) === base(U(i, log2Up(regions) bits))) &
(pmpcfg(i)(lBit) | ~privilegeService.isMachine()) & pmpcfg(i)(aBits) === NAPOT
(pmpcfg(i)(lBit) | ~machineMode) & (pmpcfg(i)(aBits) === NAPOT)
)
}
@ -315,8 +278,8 @@ class PmpPlugin(regions : Int, granularity : Int, ioRange : UInt => Bool) extend
val hits = getHits(address(31 downto cutoff))
when(~hits.orR) {
dPort.bus.rsp.allowRead := privilegeService.isMachine()
dPort.bus.rsp.allowWrite := privilegeService.isMachine()
dPort.bus.rsp.allowRead := machineMode
dPort.bus.rsp.allowWrite := machineMode
} otherwise {
dPort.bus.rsp.allowRead := getPermission(hits, rBit)
dPort.bus.rsp.allowWrite := getPermission(hits, wBit)
@ -337,7 +300,7 @@ class PmpPlugin(regions : Int, granularity : Int, ioRange : UInt => Bool) extend
val hits = getHits(address(31 downto cutoff))
when(~hits.orR) {
iPort.bus.rsp.allowExecute := privilegeService.isMachine()
iPort.bus.rsp.allowExecute := machineMode
} otherwise {
iPort.bus.rsp.allowExecute := getPermission(hits, xBit)
}

457
src/test/cpp/raw/pmp/build/pmp.asm
View File

@ -22,271 +22,244 @@ Disassembly of section .crt_section:
80000024 <test0>:
80000024: 00000e13 li t3,0
80000028: 00000f17 auipc t5,0x0
8000002c: 39cf0f13 addi t5,t5,924 # 800003c4 <fail>
8000002c: 340f0f13 addi t5,t5,832 # 80000368 <fail>
80000030: 800000b7 lui ra,0x80000
80000034: 80008237 lui tp,0x80008
80000038: deadc137 lui sp,0xdeadc
8000003c: eef10113 addi sp,sp,-273 # deadbeef <pass+0x5eadbb1f>
80000040: 0020a023 sw sp,0(ra) # 80000000 <pass+0xfffffc30>
80000044: 00222023 sw sp,0(tp) # 80008000 <pass+0x7c30>
8000003c: eef10113 addi sp,sp,-273 # deadbeef <pass+0x5eadbb7b>
80000040: 0020a023 sw sp,0(ra) # 80000000 <pass+0xfffffc8c>
80000044: 00222023 sw sp,0(tp) # 80008000 <pass+0x7c8c>
80000048: 0000a183 lw gp,0(ra)
8000004c: 36311c63 bne sp,gp,800003c4 <fail>
8000004c: 30311e63 bne sp,gp,80000368 <fail>
80000050: 00022183 lw gp,0(tp) # 0 <_start-0x80000000>
80000054: 36311863 bne sp,gp,800003c4 <fail>
80000058: 071202b7 lui t0,0x7120
80000054: 30311a63 bne sp,gp,80000368 <fail>
80000058: 071a02b7 lui t0,0x71a0
8000005c: 3a029073 csrw pmpcfg0,t0
80000060: 3a002373 csrr t1,pmpcfg0
80000064: 191f02b7 lui t0,0x191f0
80000068: 30428293 addi t0,t0,772 # 191f0304 <_start-0x66e0fcfc>
8000006c: 3a129073 csrw pmpcfg1,t0
80000070: 000f12b7 lui t0,0xf1
80000074: 90a28293 addi t0,t0,-1782 # f090a <_start-0x7ff0f6f6>
80000078: 3a229073 csrw pmpcfg2,t0
8000007c: 0f1e22b7 lui t0,0xf1e2
80000080: 90028293 addi t0,t0,-1792 # f1e1900 <_start-0x70e1e700>
80000084: 3a329073 csrw pmpcfg3,t0
80000088: 200002b7 lui t0,0x20000
8000008c: 3b029073 csrw pmpaddr0,t0
80000090: 3b002373 csrr t1,pmpaddr0
80000094: fff00293 li t0,-1
80000098: 3b129073 csrw pmpaddr1,t0
8000009c: 200022b7 lui t0,0x20002
800000a0: 3b229073 csrw pmpaddr2,t0
800000a4: 200042b7 lui t0,0x20004
800000a8: fff28293 addi t0,t0,-1 # 20003fff <_start-0x5fffc001>
800000ac: 3b329073 csrw pmpaddr3,t0
800000b0: 200042b7 lui t0,0x20004
800000b4: fff28293 addi t0,t0,-1 # 20003fff <_start-0x5fffc001>
800000b8: 3b429073 csrw pmpaddr4,t0
800000bc: 200042b7 lui t0,0x20004
800000c0: fff28293 addi t0,t0,-1 # 20003fff <_start-0x5fffc001>
800000c4: 3b529073 csrw pmpaddr5,t0
800000c8: 200022b7 lui t0,0x20002
800000cc: fff28293 addi t0,t0,-1 # 20001fff <_start-0x5fffe001>
800000d0: 3b629073 csrw pmpaddr6,t0
800000d4: 200062b7 lui t0,0x20006
800000d8: fff28293 addi t0,t0,-1 # 20005fff <_start-0x5fffa001>
800000dc: 3b729073 csrw pmpaddr7,t0
800000e0: 200d02b7 lui t0,0x200d0
800000e4: 3b829073 csrw pmpaddr8,t0
800000e8: 200e02b7 lui t0,0x200e0
800000ec: 3b929073 csrw pmpaddr9,t0
800000f0: fff00293 li t0,-1
800000f4: 3ba29073 csrw pmpaddr10,t0
800000f8: 00000293 li t0,0
800000fc: 3bb29073 csrw pmpaddr11,t0
80000100: 00000293 li t0,0
80000104: 3bc29073 csrw pmpaddr12,t0
80000064: 30629263 bne t0,t1,80000368 <fail>
80000068: 1a1902b7 lui t0,0x1a190
8000006c: 30428293 addi t0,t0,772 # 1a190304 <_start-0x65e6fcfc>
80000070: 3a129073 csrw pmpcfg1,t0
80000074: 000f12b7 lui t0,0xf1
80000078: 90a28293 addi t0,t0,-1782 # f090a <_start-0x7ff0f6f6>
8000007c: 3a229073 csrw pmpcfg2,t0
80000080: 3a202373 csrr t1,pmpcfg2
80000084: 2e629263 bne t0,t1,80000368 <fail>
80000088: 1c1e22b7 lui t0,0x1c1e2
8000008c: 90028293 addi t0,t0,-1792 # 1c1e1900 <_start-0x63e1e700>
80000090: 3a329073 csrw pmpcfg3,t0
80000094: 200002b7 lui t0,0x20000
80000098: 3b029073 csrw pmpaddr0,t0
8000009c: 3b002373 csrr t1,pmpaddr0
800000a0: 2c629463 bne t0,t1,80000368 <fail>
800000a4: fff00293 li t0,-1
800000a8: 3b129073 csrw pmpaddr1,t0
800000ac: 202002b7 lui t0,0x20200
800000b0: 3b229073 csrw pmpaddr2,t0
800000b4: 200042b7 lui t0,0x20004
800000b8: fff28293 addi t0,t0,-1 # 20003fff <_start-0x5fffc001>
800000bc: 3b329073 csrw pmpaddr3,t0
800000c0: 200042b7 lui t0,0x20004
800000c4: fff28293 addi t0,t0,-1 # 20003fff <_start-0x5fffc001>
800000c8: 3b429073 csrw pmpaddr4,t0
800000cc: 200042b7 lui t0,0x20004
800000d0: fff28293 addi t0,t0,-1 # 20003fff <_start-0x5fffc001>
800000d4: 3b529073 csrw pmpaddr5,t0
800000d8: 230002b7 lui t0,0x23000
800000dc: fff28293 addi t0,t0,-1 # 22ffffff <_start-0x5d000001>
800000e0: 3b629073 csrw pmpaddr6,t0
800000e4: 220402b7 lui t0,0x22040
800000e8: fff28293 addi t0,t0,-1 # 2203ffff <_start-0x5dfc0001>
800000ec: 3b729073 csrw pmpaddr7,t0
800000f0: 200d02b7 lui t0,0x200d0
800000f4: 3b829073 csrw pmpaddr8,t0
800000f8: 200e02b7 lui t0,0x200e0
800000fc: 3b929073 csrw pmpaddr9,t0
80000100: fff00293 li t0,-1
80000104: 3ba29073 csrw pmpaddr10,t0
80000108: 00000293 li t0,0
8000010c: 3bd29073 csrw pmpaddr13,t0
8000010c: 3bb29073 csrw pmpaddr11,t0
80000110: 00000293 li t0,0
80000114: 3be29073 csrw pmpaddr14,t0
80000114: 3bc29073 csrw pmpaddr12,t0
80000118: 00000293 li t0,0
8000011c: 3bf29073 csrw pmpaddr15,t0
80000120: 00c10137 lui sp,0xc10
80000124: fee10113 addi sp,sp,-18 # c0ffee <_start-0x7f3f0012>
80000128: 0020a023 sw sp,0(ra)
8000012c: 00222023 sw sp,0(tp) # 0 <_start-0x80000000>
80000130: 0000a183 lw gp,0(ra)
80000134: 28311863 bne sp,gp,800003c4 <fail>
80000138: 00000193 li gp,0
8000013c: 00022183 lw gp,0(tp) # 0 <_start-0x80000000>
80000140: 28311263 bne sp,gp,800003c4 <fail>
8000011c: 3bd29073 csrw pmpaddr13,t0
80000120: 00000293 li t0,0
80000124: 3be29073 csrw pmpaddr14,t0
80000128: fff00293 li t0,-1
8000012c: 3bf29073 csrw pmpaddr15,t0
80000130: 00c10137 lui sp,0xc10
80000134: fee10113 addi sp,sp,-18 # c0ffee <_start-0x7f3f0012>
80000138: 0020a023 sw sp,0(ra)
8000013c: 00222023 sw sp,0(tp) # 0 <_start-0x80000000>
80000140: 0000a183 lw gp,0(ra)
80000144: 22311263 bne sp,gp,80000368 <fail>
80000148: 00000193 li gp,0
8000014c: 00022183 lw gp,0(tp) # 0 <_start-0x80000000>
80000150: 20311c63 bne sp,gp,80000368 <fail>
80000144 <test1>:
80000144: 00100e13 li t3,1
80000148: 00000f17 auipc t5,0x0
8000014c: 27cf0f13 addi t5,t5,636 # 800003c4 <fail>
80000150: 079212b7 lui t0,0x7921
80000154: 80828293 addi t0,t0,-2040 # 7920808 <_start-0x786df7f8>
80000158: 3a029073 csrw pmpcfg0,t0
8000015c: 3a002373 csrr t1,pmpcfg0
80000160: 26629263 bne t0,t1,800003c4 <fail>
80000164: 800080b7 lui ra,0x80008
80000168: deadc137 lui sp,0xdeadc
8000016c: eef10113 addi sp,sp,-273 # deadbeef <pass+0x5eadbb1f>
80000170: 0020a023 sw sp,0(ra) # 80008000 <pass+0x7c30>
80000174: 00000f17 auipc t5,0x0
80000178: 010f0f13 addi t5,t5,16 # 80000184 <test2>
8000017c: 0000a183 lw gp,0(ra)
80000180: 2440006f j 800003c4 <fail>
80000154 <test1>:
80000154: 00100e13 li t3,1
80000158: 00000f17 auipc t5,0x0
8000015c: 210f0f13 addi t5,t5,528 # 80000368 <fail>
80000160: 079a12b7 lui t0,0x79a1
80000164: 80828293 addi t0,t0,-2040 # 79a0808 <_start-0x7865f7f8>
80000168: 3a029073 csrw pmpcfg0,t0
8000016c: 3a002373 csrr t1,pmpcfg0
80000170: 1e629c63 bne t0,t1,80000368 <fail>
80000174: 808000b7 lui ra,0x80800
80000178: deadc137 lui sp,0xdeadc
8000017c: eef10113 addi sp,sp,-273 # deadbeef <pass+0x5eadbb7b>
80000180: 0020a023 sw sp,0(ra) # 80800000 <pass+0x7ffc8c>
80000184: 00000f17 auipc t5,0x0
80000188: 010f0f13 addi t5,t5,16 # 80000194 <test2>
8000018c: 0000a183 lw gp,0(ra)
80000190: 1d80006f j 80000368 <fail>
80000184 <test2>:
80000184: 00200e13 li t3,2
80000188: 00000f17 auipc t5,0x0
8000018c: 23cf0f13 addi t5,t5,572 # 800003c4 <fail>
80000190: 071202b7 lui t0,0x7120
80000194: 3a029073 csrw pmpcfg0,t0
80000198: 3a002373 csrr t1,pmpcfg0
8000019c: 22628463 beq t0,t1,800003c4 <fail>
800001a0: 200042b7 lui t0,0x20004
800001a4: fff28293 addi t0,t0,-1 # 20003fff <_start-0x5fffc001>
800001a8: 3b305073 csrwi pmpaddr3,0
800001ac: 3b302373 csrr t1,pmpaddr3
800001b0: 20031a63 bnez t1,800003c4 <fail>
800001b4: 20628863 beq t0,t1,800003c4 <fail>
800001b8: 200022b7 lui t0,0x20002
80000194 <test2>:
80000194: 00200e13 li t3,2
80000198: 00000f17 auipc t5,0x0
8000019c: 1d0f0f13 addi t5,t5,464 # 80000368 <fail>
800001a0: 071a02b7 lui t0,0x71a0
800001a4: 3a029073 csrw pmpcfg0,t0
800001a8: 3a002373 csrr t1,pmpcfg0
800001ac: 1a628e63 beq t0,t1,80000368 <fail>
800001b0: 3b305073 csrwi pmpaddr3,0
800001b4: 3b302373 csrr t1,pmpaddr3
800001b8: 1a031863 bnez t1,80000368 <fail>
800001bc: 3b205073 csrwi pmpaddr2,0
800001c0: 3b202373 csrr t1,pmpaddr2
800001c4: 20030063 beqz t1,800003c4 <fail>
800001c8: 1e629e63 bne t0,t1,800003c4 <fail>
800001cc: 800080b7 lui ra,0x80008
800001d0: deadc137 lui sp,0xdeadc
800001d4: eef10113 addi sp,sp,-273 # deadbeef <pass+0x5eadbb1f>
800001d8: 0020a023 sw sp,0(ra) # 80008000 <pass+0x7c30>
800001dc: 00000f17 auipc t5,0x0
800001e0: 010f0f13 addi t5,t5,16 # 800001ec <test3>
800001e4: 0000a183 lw gp,0(ra)
800001e8: 1dc0006f j 800003c4 <fail>
800001c4: 1a030263 beqz t1,80000368 <fail>
800001c8: 808000b7 lui ra,0x80800
800001cc: deadc137 lui sp,0xdeadc
800001d0: eef10113 addi sp,sp,-273 # deadbeef <pass+0x5eadbb7b>
800001d4: 0020a023 sw sp,0(ra) # 80800000 <pass+0x7ffc8c>
800001d8: 00000f17 auipc t5,0x0
800001dc: 010f0f13 addi t5,t5,16 # 800001e8 <test3>
800001e0: 0000a183 lw gp,0(ra)
800001e4: 1840006f j 80000368 <fail>
800001ec <test3>:
800001ec: 00300e13 li t3,3
800001f0: 00000f17 auipc t5,0x0
800001f4: 1d4f0f13 addi t5,t5,468 # 800003c4 <fail>
800001f8: 00ff02b7 lui t0,0xff0
800001fc: 3b32a073 csrs pmpaddr3,t0
80000200: 3b302373 csrr t1,pmpaddr3
80000204: 1c629063 bne t0,t1,800003c4 <fail>
80000208: 0ff00293 li t0,255
8000020c: 3b32a073 csrs pmpaddr3,t0
80000210: 3b302373 csrr t1,pmpaddr3
80000214: 00ff02b7 lui t0,0xff0
80000218: 0ff28293 addi t0,t0,255 # ff00ff <_start-0x7f00ff01>
8000021c: 1a629463 bne t0,t1,800003c4 <fail>
80000220: 00ff02b7 lui t0,0xff0
80000224: 3b32b073 csrc pmpaddr3,t0
80000228: 3b302373 csrr t1,pmpaddr3
8000022c: 0ff00293 li t0,255
80000230: 18629a63 bne t0,t1,800003c4 <fail>
80000234: 00ff02b7 lui t0,0xff0
80000238: 0ff28293 addi t0,t0,255 # ff00ff <_start-0x7f00ff01>
8000023c: 3a02b073 csrc pmpcfg0,t0
80000240: 3a002373 csrr t1,pmpcfg0
80000244: 079202b7 lui t0,0x7920
80000248: 16629e63 bne t0,t1,800003c4 <fail>
8000024c: 00ff02b7 lui t0,0xff0
80000250: 70728293 addi t0,t0,1799 # ff0707 <_start-0x7f00f8f9>
80000254: 3a02a073 csrs pmpcfg0,t0
80000258: 3a002373 csrr t1,pmpcfg0
8000025c: 079202b7 lui t0,0x7920
80000260: 70728293 addi t0,t0,1799 # 7920707 <_start-0x786df8f9>
80000264: 16629063 bne t0,t1,800003c4 <fail>
800001e8 <test3>:
800001e8: 00300e13 li t3,3
800001ec: 00000f17 auipc t5,0x0
800001f0: 17cf0f13 addi t5,t5,380 # 80000368 <fail>
800001f4: 00ff02b7 lui t0,0xff0
800001f8: 3b32a073 csrs pmpaddr3,t0
800001fc: 3b302373 csrr t1,pmpaddr3
80000200: 16629463 bne t0,t1,80000368 <fail>
80000204: 0ff00293 li t0,255
80000208: 3b32a073 csrs pmpaddr3,t0
8000020c: 3b302373 csrr t1,pmpaddr3
80000210: 00ff02b7 lui t0,0xff0
80000214: 0ff28293 addi t0,t0,255 # ff00ff <_start-0x7f00ff01>
80000218: 14629863 bne t0,t1,80000368 <fail>
8000021c: 00ff02b7 lui t0,0xff0
80000220: 3b32b073 csrc pmpaddr3,t0
80000224: 3b302373 csrr t1,pmpaddr3
80000228: 0ff00293 li t0,255
8000022c: 12629e63 bne t0,t1,80000368 <fail>
80000230: 00ff02b7 lui t0,0xff0
80000234: 0ff28293 addi t0,t0,255 # ff00ff <_start-0x7f00ff01>
80000238: 3a02b073 csrc pmpcfg0,t0
8000023c: 3a002373 csrr t1,pmpcfg0
80000240: 079a02b7 lui t0,0x79a0
80000244: 12629263 bne t0,t1,80000368 <fail>
80000248: 00ff02b7 lui t0,0xff0
8000024c: 70728293 addi t0,t0,1799 # ff0707 <_start-0x7f00f8f9>
80000250: 3a02a073 csrs pmpcfg0,t0
80000254: 3a002373 csrr t1,pmpcfg0
80000258: 079a02b7 lui t0,0x79a0
8000025c: 70728293 addi t0,t0,1799 # 79a0707 <_start-0x7865f8f9>
80000260: 10629463 bne t0,t1,80000368 <fail>
80000268 <test4>:
80000268: 00400e13 li t3,4
8000026c: 00000f17 auipc t5,0x0
80000270: 158f0f13 addi t5,t5,344 # 800003c4 <fail>
80000274: 00000117 auipc sp,0x0
80000278: 01010113 addi sp,sp,16 # 80000284 <test5>
8000027c: 34111073 csrw mepc,sp
80000280: 30200073 mret
80000264 <test4>:
80000264: 00400e13 li t3,4
80000268: 00000f17 auipc t5,0x0
8000026c: 100f0f13 addi t5,t5,256 # 80000368 <fail>
80000270: 00000117 auipc sp,0x0
80000274: 01010113 addi sp,sp,16 # 80000280 <test5>
80000278: 34111073 csrw mepc,sp
8000027c: 30200073 mret
80000284 <test5>:
80000284: 00500e13 li t3,5
80000288: 00000f17 auipc t5,0x0
8000028c: 13cf0f13 addi t5,t5,316 # 800003c4 <fail>
80000290: deadc137 lui sp,0xdeadc
80000294: eef10113 addi sp,sp,-273 # deadbeef <pass+0x5eadbb1f>
80000298: 800080b7 lui ra,0x80008
8000029c: 0020a023 sw sp,0(ra) # 80008000 <pass+0x7c30>
800002a0: 00000f17 auipc t5,0x0
800002a4: 010f0f13 addi t5,t5,16 # 800002b0 <test6>
800002a8: 0000a183 lw gp,0(ra)
800002ac: 1180006f j 800003c4 <fail>
80000280 <test5>:
80000280: 00500e13 li t3,5
80000284: 00000f17 auipc t5,0x0
80000288: 0e4f0f13 addi t5,t5,228 # 80000368 <fail>
8000028c: deadc137 lui sp,0xdeadc
80000290: eef10113 addi sp,sp,-273 # deadbeef <pass+0x5eadbb7b>
80000294: 808000b7 lui ra,0x80800
80000298: 0020a023 sw sp,0(ra) # 80800000 <pass+0x7ffc8c>
8000029c: 00000f17 auipc t5,0x0
800002a0: 010f0f13 addi t5,t5,16 # 800002ac <test6>
800002a4: 0000a183 lw gp,0(ra)
800002a8: 0c00006f j 80000368 <fail>
800002b0 <test6>:
800002b0: 00600e13 li t3,6
800002b4: 00000f17 auipc t5,0x0
800002b8: 110f0f13 addi t5,t5,272 # 800003c4 <fail>
800002bc: deadc137 lui sp,0xdeadc
800002c0: eef10113 addi sp,sp,-273 # deadbeef <pass+0x5eadbb1f>
800002c4: 800000b7 lui ra,0x80000
800002c8: 0020a023 sw sp,0(ra) # 80000000 <pass+0xfffffc30>
800002cc: 0000a183 lw gp,0(ra)
800002d0: 0e311a63 bne sp,gp,800003c4 <fail>
800002ac <test6>:
800002ac: 00600e13 li t3,6
800002b0: 00000f17 auipc t5,0x0
800002b4: 0b8f0f13 addi t5,t5,184 # 80000368 <fail>
800002b8: deadc137 lui sp,0xdeadc
800002bc: eef10113 addi sp,sp,-273 # deadbeef <pass+0x5eadbb7b>
800002c0: 880000b7 lui ra,0x88000
800002c4: 0020a023 sw sp,0(ra) # 88000000 <pass+0x7fffc8c>
800002c8: 0000a183 lw gp,0(ra)
800002d4 <test7>:
800002d4: 00700e13 li t3,7
800002d8: 00000f17 auipc t5,0x0
800002dc: 0ecf0f13 addi t5,t5,236 # 800003c4 <fail>
800002e0: 800400b7 lui ra,0x80040
800002e4: 0000a183 lw gp,0(ra) # 80040000 <pass+0x3fc30>
800002e8: 00000f17 auipc t5,0x0
800002ec: 010f0f13 addi t5,t5,16 # 800002f8 <test8>
800002f0: 0030a023 sw gp,0(ra)
800002f4: 0d00006f j 800003c4 <fail>
800002cc <test7>:
800002cc: 00700e13 li t3,7
800002d0: 00000f17 auipc t5,0x0
800002d4: 098f0f13 addi t5,t5,152 # 80000368 <fail>
800002d8: 890000b7 lui ra,0x89000
800002dc: ff008093 addi ra,ra,-16 # 88fffff0 <pass+0x8fffc7c>
800002e0: 0000a183 lw gp,0(ra)
800002e4: 00000f17 auipc t5,0x0
800002e8: 010f0f13 addi t5,t5,16 # 800002f4 <test8a>
800002ec: 0030a023 sw gp,0(ra)
800002f0: 0780006f j 80000368 <fail>
800002f8 <test8>:
800002f8: 00800e13 li t3,8
800002fc: 00000f17 auipc t5,0x0
80000300: 0c8f0f13 addi t5,t5,200 # 800003c4 <fail>
80000304: deadc137 lui sp,0xdeadc
80000308: eef10113 addi sp,sp,-273 # deadbeef <pass+0x5eadbb1f>
8000030c: 803400b7 lui ra,0x80340
80000310: ff808093 addi ra,ra,-8 # 8033fff8 <pass+0x33fc28>
80000314: 00222023 sw sp,0(tp) # 0 <_start-0x80000000>
80000318: 00000f17 auipc t5,0x0
8000031c: 010f0f13 addi t5,t5,16 # 80000328 <test9>
80000320: 00022183 lw gp,0(tp) # 0 <_start-0x80000000>
80000324: 0a00006f j 800003c4 <fail>
800002f4 <test8a>:
800002f4: 00800e13 li t3,8
800002f8: 00000f17 auipc t5,0x0
800002fc: 014f0f13 addi t5,t5,20 # 8000030c <test8b>
80000300: 00100493 li s1,1
80000304: 3a305073 csrwi pmpcfg3,0
80000308: 0600006f j 80000368 <fail>
80000328 <test9>:
80000328: 00900e13 li t3,9
8000032c: 00000f17 auipc t5,0x0
80000330: 098f0f13 addi t5,t5,152 # 800003c4 <fail>
80000334: 803800b7 lui ra,0x80380
80000338: ff808093 addi ra,ra,-8 # 8037fff8 <pass+0x37fc28>
8000033c: 0000a183 lw gp,0(ra)
80000340: 00000f17 auipc t5,0x0
80000344: 010f0f13 addi t5,t5,16 # 80000350 <test10a>
80000348: 0030a023 sw gp,0(ra)
8000034c: 0780006f j 800003c4 <fail>
8000030c <test8b>:
8000030c: 00800e13 li t3,8
80000310: 1c1e22b7 lui t0,0x1c1e2
80000314: 90028293 addi t0,t0,-1792 # 1c1e1900 <_start-0x63e1e700>
80000318: 3a302373 csrr t1,pmpcfg3
8000031c: 04629663 bne t0,t1,80000368 <fail>
80000350 <test10a>:
80000350: 00a00e13 li t3,10
80000354: 00000f17 auipc t5,0x0
80000358: 014f0f13 addi t5,t5,20 # 80000368 <test10b>
8000035c: 00100493 li s1,1
80000360: 3a305073 csrwi pmpcfg3,0
80000364: 0600006f j 800003c4 <fail>
80000320 <test9a>:
80000320: 00900e13 li t3,9
80000324: 00000f17 auipc t5,0x0
80000328: 044f0f13 addi t5,t5,68 # 80000368 <fail>
8000032c: 00000493 li s1,0
80000330: 00000117 auipc sp,0x0
80000334: 01010113 addi sp,sp,16 # 80000340 <test9b>
80000338: 34111073 csrw mepc,sp
8000033c: 30200073 mret
80000368 <test10b>:
80000368: 00a00e13 li t3,10
8000036c: 0f1e22b7 lui t0,0xf1e2
80000370: 90028293 addi t0,t0,-1792 # f1e1900 <_start-0x70e1e700>
80000374: 3a302373 csrr t1,pmpcfg3
80000378: 04629663 bne t0,t1,800003c4 <fail>
80000340 <test9b>:
80000340: 00900e13 li t3,9
80000344: 00000f17 auipc t5,0x0
80000348: 014f0f13 addi t5,t5,20 # 80000358 <test9c>
8000034c: 00100493 li s1,1
80000350: 3ba05073 csrwi pmpaddr10,0
80000354: 0140006f j 80000368 <fail>
8000037c <test11a>:
8000037c: 00b00e13 li t3,11
80000380: 00000f17 auipc t5,0x0
80000384: 044f0f13 addi t5,t5,68 # 800003c4 <fail>
80000388: 00000493 li s1,0
8000038c: 00000117 auipc sp,0x0
80000390: 01010113 addi sp,sp,16 # 8000039c <test11b>
80000394: 34111073 csrw mepc,sp
80000398: 30200073 mret
80000358 <test9c>:
80000358: 00900e13 li t3,9
8000035c: fff00293 li t0,-1
80000360: 3ba02373 csrr t1,pmpaddr10
80000364: 00628863 beq t0,t1,80000374 <pass>
8000039c <test11b>:
8000039c: 00b00e13 li t3,11
800003a0: 00000f17 auipc t5,0x0
800003a4: 014f0f13 addi t5,t5,20 # 800003b4 <test11c>
800003a8: 00100493 li s1,1
800003ac: 3ba05073 csrwi pmpaddr10,0
800003b0: 0140006f j 800003c4 <fail>
80000368 <fail>:
80000368: f0100137 lui sp,0xf0100
8000036c: f2410113 addi sp,sp,-220 # f00fff24 <pass+0x700ffbb0>
80000370: 01c12023 sw t3,0(sp)
800003b4 <test11c>:
800003b4: 00b00e13 li t3,11
800003b8: fff00293 li t0,-1
800003bc: 3ba02373 csrr t1,pmpaddr10
800003c0: 00628863 beq t0,t1,800003d0 <pass>
800003c4 <fail>:
800003c4: f0100137 lui sp,0xf0100
800003c8: f2410113 addi sp,sp,-220 # f00fff24 <pass+0x700ffb54>
800003cc: 01c12023 sw t3,0(sp)
800003d0 <pass>:
800003d0: f0100137 lui sp,0xf0100
800003d4: f2010113 addi sp,sp,-224 # f00fff20 <pass+0x700ffb50>
800003d8: 00012023 sw zero,0(sp)
80000374 <pass>:
80000374: f0100137 lui sp,0xf0100
80000378: f2010113 addi sp,sp,-224 # f00fff20 <pass+0x700ffbac>
8000037c: 00012023 sw zero,0(sp)

BIN
src/test/cpp/raw/pmp/build/pmp.elf
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112
src/test/cpp/raw/pmp/build/pmp.hex
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@ -1,65 +1,59 @@
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:10017000639C621EB700808037C1ADDE1301F1EED3
:1001800023A02000170F0000130F0F0183A1000010
:100190006F00801D130E2000170F0000130F0F1D9E
:1001A000B7021A077390023A7323003A638E621AF9
:1001B0007350303B7323303B6318031A7350203B5A
:1001C0007323203B6302031AB700808037C1ADDE82
:1001D0001301F1EE23A02000170F0000130F0F01F1
:1001E00083A100006F004018130E3000170F0000AD
:1001F000130FCF17B702FF0073A0323B7323303BBE
:10020000639462169302F00F73A0323B7323303B6A
:10021000B702FF009382F20F63986214B702FF00E7
:1002200073B0323B7323303B9302F00F639E621234
:10023000B702FF009382F20F73B0023A7323003AC1
:10024000B7029A0763926212B702FF00938272703C
:1002500073A0023A7323003AB7029A07938272702E
:1002600063946210130E4000170F0000130F0F105D
:1002700017010000130101017310113473002030C5
:10028000130E5000170F0000130F4F0E37C1ADDED5
:100290001301F1EEB700808023A02000170F0000AB
:1002A000130F0F0183A100006F00000C130E6000FC
:1002B000170F0000130F8F0B37C1ADDE1301F1EEE6
:1002C000B700008823A0200083A10000130E700057
:1002D000170F0000130F8F09B7000089938000FFEC
:1002E00083A10000170F0000130F0F0123A030009F
:1002F0006F008007130E8000170F0000130F4F01CF
:10030000930410007350303A6F000006130E800003
:10031000B7221E1C938202907323303A63966204C4
:10032000130E9000170F0000130F4F0493040000EA
:100330001701000013010101731011347300203004
:10034000130E9000170F0000130F4F0193041000BD
:100350007350A03B6F004001130E90009302F0FF1A
:100360007323A03B63886200370110F0130141F250
:100370002320C101370110F0130101F223200100F5
:040000058000000077
:00000001FF

12
src/test/cpp/raw/pmp/build/pmp.map
View File

@ -15,19 +15,19 @@ LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/8.3.0/../../../../riscv64-unk
END GROUP
LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/8.3.0/rv32i/ilp32/libgcc.a
.crt_section 0x0000000080000000 0x3dc
.crt_section 0x0000000080000000 0x380
0x0000000080000000 . = ALIGN (0x4)
*crt.o(.text)
.text 0x0000000080000000 0x3dc build/src/crt.o
.text 0x0000000080000000 0x380 build/src/crt.o
0x0000000080000000 _start
0x0000000080000014 trap
OUTPUT(build/pmp.elf elf32-littleriscv)
.data 0x00000000800003dc 0x0
.data 0x00000000800003dc 0x0 build/src/crt.o
.data 0x0000000080000380 0x0
.data 0x0000000080000380 0x0 build/src/crt.o
.bss 0x00000000800003dc 0x0
.bss 0x00000000800003dc 0x0 build/src/crt.o
.bss 0x0000000080000380 0x0
.bss 0x0000000080000380 0x0 build/src/crt.o
.riscv.attributes
0x0000000000000000 0x1a

89
src/test/cpp/raw/pmp/src/crt.S
View File

@ -10,7 +10,7 @@
#define PMPCFG0 0x071a0000
#define PMPCFG0_ 0x079a0808
#define PMPCFG1 0x191f0304
#define PMPCFG1 0x1a190304
#define PMPCFG2 0x000f090a
#define PMPCFG3 0x1c1e1900
@ -20,8 +20,8 @@
#define PMPADDR3 0x20003fff // OFF RWX -> 0x00000000 OFF RWX (test2)
#define PMPADDR4 0x20003fff // OFF X
#define PMPADDR5 0x20003fff // OFF RW
#define PMPADDR6 0x20001fff // NAPOT RWX
#define PMPADDR7 0x20005fff // NAPOT R
#define PMPADDR6 0x22ffffff // NAPOT R
#define PMPADDR7 0x2203ffff // NAPOT W
#define PMPADDR8 0x200d0000 // TOR W
#define PMPADDR9 0x200e0000 // TOR R
#define PMPADDR10 0xffffffff // TOR RWX
@ -29,7 +29,7 @@
#define PMPADDR12 0x00000000 // OFF
#define PMPADDR13 0x00000000 // NAPOT R
#define PMPADDR14 0x00000000 // NAPOT WX
#define PMPADDR15 0x000001ff // NAPOT X
#define PMPADDR15 0xffffffff // NAPOT X
.global _start
_start:
@ -129,9 +129,9 @@ test1:
bne x5, x6, fail
li x1, 0x80800000
li x2, 0xdeadbeef
sw x2, 0x0(x1) // should be OK (write 0x80800000)
sw x2, 0x0(x1) // should be OK (write region 2)
la TRAP_RETURN, test2
lw x3, 0x0(x1) // should fault (read 0x80800000)
lw x3, 0x0(x1) // should fault (read region 2)
j fail
// "unlock" region 2, attempt read/write from machine mode
@ -150,9 +150,9 @@ test2:
beqz x6, fail
li x1, 0x80800000
li x2, 0xdeadbeef
sw x2, 0x0(x1) // should still be OK (write 0x80800000)
sw x2, 0x0(x1) // should still be OK (write region 2)
la TRAP_RETURN, test3
lw x3, 0x0(x1) // should still fault (read 0x80800000)
lw x3, 0x0(x1) // should still fault (read region 2)
j fail
// verify masked CSR read/write operations
@ -184,99 +184,78 @@ test3:
li x5, 0x079a0707
bne x5, x6, fail
// jump into user mode
// jump into U-mode
test4:
li TEST_ID, 4
la TRAP_RETURN, fail
la x2, test5
csrw mepc, x2
# j pass
mret
// attempt to read/write region 2 from user mode
// attempt to read/write the locked region from U-mode
test5:
li TEST_ID, 5
la TRAP_RETURN, fail
li x2, 0xdeadbeef
li x1, 0x80800000
sw x2, 0x0(x1) // should be OK (write 0x80800000)
sw x2, 0x0(x1) // should be OK (write region 2)
la TRAP_RETURN, test6
lw x3, 0x0(x1) // should fault (read 0x80800000)
lw x3, 0x0(x1) // should fault (read region 2)
j fail
// attempt to read/write other regions from user mode
// attempt to read/write overlapping regions from U-mode
test6:
li TEST_ID, 6
la TRAP_RETURN, fail
la TRAP_RETURN, fail
li x2, 0xdeadbeef
li x1, 0x80000000
sw x2, 0x0(x1)
lw x3, 0x0(x1)
bne x2, x3, fail // should be OK (read/write 0x80000000)
li x1, 0x88000000
sw x2, 0x0(x1) // should be OK (write region 6/7)
lw x3, 0x0(x1) // should be OK (write region 6/7)
test7:
li TEST_ID, 7
la TRAP_RETURN, fail
li x1, 0x80040000
lw x3, 0x0(x1) // should be OK (read 0x80040000)
la TRAP_RETURN, test8
sw x3, 0x0(x1) // should fault (write 0x80040000)
j fail
test8:
li TEST_ID, 8
la TRAP_RETURN, fail
li x2, 0xdeadbeef
li x1, 0x8033fff8
sw x2, 0x0(x4) // should be OK (write region 8)
la TRAP_RETURN, test9
lw x3, 0x0(x4) // should fault (read region 8)
j fail
test9:
li TEST_ID, 9
la TRAP_RETURN, fail
li x1, 0x8037fff8
lw x3, 0x0(x1) // should be OK (read region 9)
la TRAP_RETURN, test10a
sw x3, 0x0(x1) // should fault (write region 9)
li x1, 0x88fffff0
lw x3, 0x0(x1) // should be OK (read region 6)
la TRAP_RETURN, test8a
sw x3, 0x0(x1) // should fault (write region 6)
j fail
// attempt to write a pmpcfg# register from U-mode
test10a:
li TEST_ID, 10
la TRAP_RETURN, test10b
test8a:
li TEST_ID, 8
la TRAP_RETURN, test8b
li TRAP_EXIT, 0x1
csrwi pmpcfg3, 0x0
j fail
// check the result from M-mode
test10b:
li TEST_ID, 10
test8b:
li TEST_ID, 8
li x5, PMPCFG3
csrr x6, pmpcfg3
bne x5, x6, fail
// jump back into U-mode
test11a:
li TEST_ID, 11
test9a:
li TEST_ID, 9
la TRAP_RETURN, fail
li TRAP_EXIT, 0x0
la x2, test11b
la x2, test9b
csrw mepc, x2
mret
// attempt to write a pmpaddr# register from U-mode
test11b:
li TEST_ID, 11
la TRAP_RETURN, test11c
test9b:
li TEST_ID, 9
la TRAP_RETURN, test9c
li TRAP_EXIT, 0x1
csrwi pmpaddr10, 0x0
j fail
// check the result from M-mode
test11c:
li TEST_ID, 11
test9c:
li TEST_ID, 9
li x5, PMPADDR10
csrr x6, pmpaddr10
beq x5, x6, pass

1
src/test/scala/vexriscv/TestIndividualFeatures.scala
View File

@ -520,6 +520,7 @@ class MmuPmpDimension extends VexRiscvDimension("DBus") {
override def applyOn(config: VexRiscvConfig): Unit = {
config.plugins += new PmpPlugin(
regions = 16,
granularity = 32,
ioRange = _ (31 downto 28) === 0xF
)
}