Fix SMP compile-time error when disabling supervisor
When generating SMP configuration with supervisor disable, the compiler stucks at waiting for the signal from `externalSupervisorInterrupt`, which is generated conditionally based on `withSupervisor` option.
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@ -53,6 +53,11 @@ case class VexRiscvConfig(){
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case None => false
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case None => false
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}
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}
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def withSupervisor = find(classOf[CsrPlugin]) match {
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case Some(x) => x.config.supervisorGen
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case None => false
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}
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def FLEN = if(withRvd) 64 else if(withRvf) 32 else 0
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def FLEN = if(withRvd) 64 else if(withRvf) 32 else 0
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//Default Stageables
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//Default Stageables
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@ -206,7 +206,9 @@ class VexRiscvSmpClusterWithPeripherals(p : VexRiscvSmpClusterParameter) extends
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plic.priorityWidth.load(2)
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plic.priorityWidth.load(2)
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plic.mapping.load(PlicMapping.sifive)
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plic.mapping.load(PlicMapping.sifive)
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plic.addTarget(core.cpu.externalInterrupt)
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plic.addTarget(core.cpu.externalInterrupt)
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plic.addTarget(core.cpu.externalSupervisorInterrupt)
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if(core.cpu.config.withSupervisor) {
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plic.addTarget(core.cpu.externalSupervisorInterrupt)
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}
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List(clint.logic, core.cpu.logic).produce {
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List(clint.logic, core.cpu.logic).produce {
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for (plugin <- core.cpu.config.plugins) plugin match {
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for (plugin <- core.cpu.config.plugins) plugin match {
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case plugin: CsrPlugin if plugin.utime != null => plugin.utime := clint.logic.io.time
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case plugin: CsrPlugin if plugin.utime != null => plugin.utime := clint.logic.io.time
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