Add Murax in the readme
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README.md
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README.md
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- [Interactive debug of the simulated CPU via GDB OpenOCD and Verilator](#interactive-debug-of-the-simulated-cpu-via-gdb-openocd-and-verilator)
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- [Using eclipse to run the software and debug it](#using-eclipse-to-run-the-software-and-debug-it)
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- [Briey SoC](#briey-soc)
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- [Murax SoC](#murax-soc)
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- [Build the RISC-V GCC](#build-the-risc-v-gcc)
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- [CPU parametrization and instantiation example](#cpu-parametrization-and-instantiation-example)
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- [Add a custom instruction to the CPU via the plugin system](#add-a-custom-instruction-to-the-cpu-via-the-plugin-system)
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@ -39,7 +40,9 @@ The hardware description of this CPU is done by using an very software oriented
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## Area usage and maximal frequency
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The following number where obtains by synthesis the CPU as toplevel without any specific synthesis option to save area or to get better maximal frequency (neutral).
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The following number where obtains by synthesis the CPU as toplevel without any specific synthesis option to save area or to get better maximal frequency (neutral).<br>
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The clock constraint is set to a unattainable value, which tends to increase the design area.<br>
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The used CPU corresponding configuration can be find in src/scala/vexriscv/demo.
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```
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There is some measurements of Briey SoC timings and area :
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```
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Artix 7 -> 230 Mhz 3551 LUT 3612 FF
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Cyclone V -> 126 Mhz 2,608 ALMs
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Cyclone IV -> 117 Mhz 5,196 LUT 3,784 FF
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Cyclone II -> 102 Mhz 5,321 LUT 3,787 FF
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Artix 7 -> 256 Mhz 3302 LUT 3524 FF
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Cyclone V -> 126 Mhz 2,295 ALMs
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Cyclone IV -> 121 Mhz 4,781 LUT 3,713 FF
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Cyclone II -> 104 Mhz 4,902 LUT 3,718 FF
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```
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## Murax SoC
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Murax is a very light SoC (fit in ICE40 FPGA) which could work without any external component.
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- ICE40-hx8k + icestorm => 53 Mhz, 2142 LC
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- 0.37 DMIPS/Mhz
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- 8 kB of on-chip ram
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- JTAG debugger (eclipse/GDB/openocd ready)
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- Interrupt support
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- APB bus for peripherals
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- 32 GPIO pin
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- one 16 bits prescaler, two 16 bits timers
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You can find its implementation there : src/main/scala/vexriscv/demo/Murax.scala
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To generate the Murax SoC Hardware :
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```sh
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sbt "run-main vexriscv.demo.Murax"
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```
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Then go in src/test/cpp/murax and run the simulation with :
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```sh
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make clean run
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```
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To connect OpenOCD (https://github.com/SpinalHDL/openocd_riscv) to the simulation :
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```sh
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src/openocd -f tcl/interface/jtag_tcp.cfg -c "set MURAX_CPU0_YAML /home/spinalvm/Spinal/VexRiscv/cpu0.yaml" -f tcl/target/murax.cfg
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```
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There is some measurements of Murax SoC timings and area :
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```
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Murax ->
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Artix 7 -> 307 Mhz 884 LUT 1195 FF
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Cyclone V -> 149 Mhz 655 ALMs
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Cyclone IV -> 148 Mhz 1255 LUT 1171 FF
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Cyclone II -> 121 Mhz 1259 LUT 1170 FF
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ICE40-HX -> 53 Mhz 2142 LC (icestorm)
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```
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## Build the RISC-V GCC
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