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VexRiscv
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regression fix hex << dec #46

This commit is contained in:
Dolu1990 2018-12-09 16:37:16 +01:00
parent 1fbb81a4d9
commit 281d61bbe1
1 changed files with 4 additions and 4 deletions
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8
src/test/cpp/regression/main.cpp
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@ -1064,13 +1064,13 @@ public:
#ifdef TRACE_WITH_TIME #ifdef TRACE_WITH_TIME
currentTime << currentTime <<
#endif #endif
" PC " << hex << setw(8) << top->VexRiscv->writeBack_PC << " : reg[" << dec << setw(2) << (uint32_t)top->VexRiscv->writeBack_RegFilePlugin_regFileWrite_payload_address << "] = " << hex << setw(8) << top->VexRiscv->writeBack_RegFilePlugin_regFileWrite_payload_data << endl; " PC " << hex << setw(8) << top->VexRiscv->writeBack_PC << " : reg[" << dec << setw(2) << (uint32_t)top->VexRiscv->writeBack_RegFilePlugin_regFileWrite_payload_address << "] = " << hex << setw(8) << top->VexRiscv->writeBack_RegFilePlugin_regFileWrite_payload_data << dec << endl;
} else { } else {
regTraces << regTraces <<
#ifdef TRACE_WITH_TIME #ifdef TRACE_WITH_TIME
currentTime << currentTime <<
#endif #endif
" PC " << hex << setw(8) << top->VexRiscv->writeBack_PC << endl; " PC " << hex << setw(8) << top->VexRiscv->writeBack_PC << dec << endl;
} }
if(riscvRefEnable) if(rfWriteValid != riscvRef.rfWriteValid || if(riscvRefEnable) if(rfWriteValid != riscvRef.rfWriteValid ||
(rfWriteValid && (rfWriteAddress!= riscvRef.rfWriteAddress || rfWriteData!= riscvRef.rfWriteData))){ (rfWriteValid && (rfWriteAddress!= riscvRef.rfWriteAddress || rfWriteData!= riscvRef.rfWriteData))){
@ -1118,7 +1118,7 @@ public:
staticMutex.unlock(); staticMutex.unlock();
} catch (const std::exception& e) { } catch (const std::exception& e) {
staticMutex.lock(); staticMutex.lock();
cout << "FAIL " << name << " at PC=" << hex << setw(8) << top->VexRiscv->writeBack_PC << endl; //<< " seed : " << seed << cout << "FAIL " << name << " at PC=" << hex << setw(8) << top->VexRiscv->writeBack_PC << dec << endl; //<< " seed : " << seed <<
cycles += instanceCycles; cycles += instanceCycles;
staticMutex.unlock(); staticMutex.unlock();
failed = true; failed = true;
@ -2147,7 +2147,7 @@ public:
virtual void dBusAccess(uint32_t addr,bool wr, uint32_t size,uint32_t mask, uint32_t *data, bool *error) { virtual void dBusAccess(uint32_t addr,bool wr, uint32_t size,uint32_t mask, uint32_t *data, bool *error) {
Workspace::dBusAccess(addr,wr,size,mask,data,error); Workspace::dBusAccess(addr,wr,size,mask,data,error);
if(wr && addr == 0xF00FFF2C){ if(wr && addr == 0xF00FFF2C){
out32 << hex << setw(8) << std::setfill('0') << *data; out32 << hex << setw(8) << std::setfill('0') << *data << dec;
if(++out32Counter % 4 == 0) out32 << "\n"; if(++out32Counter % 4 == 0) out32 << "\n";
*error = 0; *error = 0;
} }