Reintroduce debug plugin (instruction injector need optimisations)
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@ -14,6 +14,7 @@ trait JumpService{
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trait IBusFetcher{
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def haltIt() : Unit
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def nextPc() : (Bool, UInt)
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def getInjectionPort() : Stream[Bits]
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}
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@ -35,28 +35,28 @@ object TestsWorkspace {
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// resetVector = 0x80000000l,
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// relaxedPcCalculation = false
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// ),
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// new IBusSimplePlugin(
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// interfaceKeepData = false,
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// catchAccessFault = true
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// ),
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new IBusCachedPlugin(
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config = InstructionCacheConfig(
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cacheSize = 1024*16,
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bytePerLine = 32,
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wayCount = 1,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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catchIllegalAccess = false,
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catchAccessFault = true,
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catchMemoryTranslationMiss = false,
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asyncTagMemory = false,
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twoCycleRam = false
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)//,
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new IBusSimplePlugin(
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interfaceKeepData = false,
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catchAccessFault = true
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),
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// new IBusCachedPlugin(
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// config = InstructionCacheConfig(
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// cacheSize = 1024*16,
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// bytePerLine = 32,
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// wayCount = 1,
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// addressWidth = 32,
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// cpuDataWidth = 32,
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// memDataWidth = 32,
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// catchIllegalAccess = false,
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// catchAccessFault = true,
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// catchMemoryTranslationMiss = false,
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// asyncTagMemory = false,
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// twoCycleRam = false
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// )//,
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// memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
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// portTlbSize = 4
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// )
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),
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// ),
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// new DBusSimplePlugin(
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// catchAddressMisaligned = true,
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// catchAccessFault = true,
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@ -122,7 +122,7 @@ object TestsWorkspace {
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),
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// new DivPlugin,
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new CsrPlugin(CsrPluginConfig.all(0x80000020l).copy(deterministicInteruptionEntry = false)),
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// new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))),
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new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))),
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new BranchPlugin(
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earlyBranch = true,
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catchAddressMisaligned = true,
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@ -105,6 +105,8 @@ class DebugPlugin(val debugClockDomain : ClockDomain) extends Plugin[VexRiscv] w
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var io : DebugExtensionIo = null
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val injectionAsks = ArrayBuffer[(Stage, Bool)]()
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var isInjectingOnDecode : Bool = null
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var injectionPort : Stream[Bits] = null
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override def isInjecting(stage: Stage) : Bool = if(stage == pipeline.decode) isInjectingOnDecode else False
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object IS_EBREAK extends Stageable(Bool)
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@ -126,6 +128,7 @@ class DebugPlugin(val debugClockDomain : ClockDomain) extends Plugin[VexRiscv] w
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))
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isInjectingOnDecode = Bool()
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injectionPort = pipeline.service(classOf[IBusFetcher]).getInjectionPort()
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}
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@ -174,35 +177,39 @@ class DebugPlugin(val debugClockDomain : ClockDomain) extends Plugin[VexRiscv] w
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is(1) {
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when(io.bus.cmd.wr) {
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insertDecodeInstruction := True
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//TODO !!!!
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decode.arbitration.isValid.getDrivingReg setWhen (firstCycle)
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decode.arbitration.haltItself setWhen (secondCycle)
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io.bus.cmd.ready := !firstCycle && !secondCycle && execute.arbitration.isValid
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// decode.arbitration.isValid.getDrivingReg setWhen (firstCycle)
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// decode.arbitration.haltItself setWhen (secondCycle)
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// io.bus.cmd.ready := !firstCycle && !secondCycle && execute.arbitration.isValid
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io.bus.cmd.ready := injectionPort.fire
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}
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}
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}
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}
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Component.current.addPrePopTask(() => {
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//Check if the decode instruction is driven by a register
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val instructionDriver = try {decode.input(INSTRUCTION).getDrivingReg} catch { case _ : Throwable => null}
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if(instructionDriver != null){ //If yes =>
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//Insert the instruction by writing the "fetch to decode instruction register",
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// Work even if it need to cross some hierarchy (caches)
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instructionDriver.component.rework {
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when(insertDecodeInstruction.pull()) {
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instructionDriver := io.bus.cmd.data.pull()
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}
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}
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} else{
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//Insert the instruction via a mux in the decode stage
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when(RegNext(insertDecodeInstruction)){
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decode.input(INSTRUCTION) := RegNext(io.bus.cmd.data)
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}
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}
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})
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injectionPort.valid := RegNext(insertDecodeInstruction) init(False) clearWhen(injectionPort.fire)
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injectionPort.payload := RegNext(io.bus.cmd.data)
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// Component.current.addPrePopTask(() => {
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// //Check if the decode instruction is driven by a register
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// val instructionDriver = try {decode.input(INSTRUCTION).getDrivingReg} catch { case _ : Throwable => null}
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// if(instructionDriver != null){ //If yes =>
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// //Insert the instruction by writing the "fetch to decode instruction register",
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// // Work even if it need to cross some hierarchy (caches)
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// instructionDriver.component.rework {
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// when(insertDecodeInstruction.pull()) {
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// instructionDriver := io.bus.cmd.data.pull()
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// }
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// }
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// } else{
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// //Insert the instruction via a mux in the decode stage
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// when(RegNext(insertDecodeInstruction)){
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// decode.input(INSTRUCTION) := RegNext(io.bus.cmd.data)
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// }
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// }
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// })
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//
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when(execute.arbitration.isFiring && execute.input(IS_EBREAK)) {
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decode.arbitration.haltByOther := True
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decode.arbitration.flushAll := True
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@ -31,6 +31,12 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
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lazy val decodeNextPc = UInt(32 bits)
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def nextPc() = (False, decodeNextPc)
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var injectionPort : Stream[Bits] = null
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override def getInjectionPort() = {
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injectionPort = Stream(Bits(32 bits))
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injectionPort
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}
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var predictionJumpInterface : Flow[UInt] = null
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override def haltIt(): Unit = fetcherHalt := True
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@ -281,6 +287,14 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
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// decodeExceptionPort.code := 1
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// decodeExceptionPort.badAddr := decode.input(PC)
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// }
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if(injectionPort != null){
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injectionPort.ready := !decode.arbitration.isStuck
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when(injectionPort.valid) {
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decode.arbitration.isValid := True
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decode.insert(INSTRUCTION) := injectionPort.payload
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}
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}
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}
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prediction match {
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