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Added MMU superpage support, pass MMU tests

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This commit is contained in:
Dolu1990 2019-03-22 12:23:47 +01:00
parent af2acbd46e
commit 2b458fc642
7 changed files with 211 additions and 137 deletions
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28
src/main/scala/vexriscv/plugin/MmuPlugin.scala
View file

@ -74,9 +74,9 @@ class MmuPlugin(virtualRange : UInt => Bool,
val sortedPortsInfo = portsInfo.sortWith((a,b) => a.priority > b.priority)
case class CacheLine() extends Bundle {
val valid, exception = Bool
val virtualAddress = UInt(20 bits)
val physicalAddress = UInt(20 bits)
val valid, exception, superPage = Bool
val virtualAddress = Vec(UInt(10 bits), UInt(10 bits))
val physicalAddress = Vec(UInt(10 bits), UInt(10 bits))
val allowRead, allowWrite, allowExecute, allowUser = Bool
def init = {
@ -89,7 +89,7 @@ class MmuPlugin(virtualRange : UInt => Bool,
val ports = for (port <- sortedPortsInfo) yield new Area {
val id = port.id
val cache = Vec(Reg(CacheLine()) init, port.args.portTlbSize)
val cacheHits = cache.map(line => line.valid && line.virtualAddress === port.bus.cmd.virtualAddress(31 downto 12))
val cacheHits = cache.map(line => line.valid && line.virtualAddress(1) === port.bus.cmd.virtualAddress(31 downto 22) && (line.superPage || line.virtualAddress(0) === port.bus.cmd.virtualAddress(21 downto 12)))
val cacheHit = cacheHits.asBits.orR
val cacheLine = MuxOH(cacheHits, cache)
val privilegeService = pipeline.serviceElse(classOf[PrivilegeService], PrivilegeServiceDefault())
@ -99,7 +99,7 @@ class MmuPlugin(virtualRange : UInt => Bool,
if(!allowMachineModeMmu) requireMmuLockup clearWhen(privilegeService.isMachine(execute))
when(requireMmuLockup) {
port.bus.rsp.physicalAddress := cacheLine.physicalAddress @@ port.bus.cmd.virtualAddress(11 downto 0)
port.bus.rsp.physicalAddress := cacheLine.physicalAddress(1) @@ (cacheLine.superPage ? port.bus.cmd.virtualAddress(21 downto 12) | cacheLine.physicalAddress(0)) @@ port.bus.cmd.virtualAddress(11 downto 0)
port.bus.rsp.allowRead := cacheLine.allowRead
port.bus.rsp.allowWrite := cacheLine.allowWrite
port.bus.rsp.allowExecute := cacheLine.allowExecute
@ -132,7 +132,7 @@ class MmuPlugin(virtualRange : UInt => Bool,
val IDLE, L1_CMD, L1_RSP, L0_CMD, L0_RSP = newElement()
}
val state = RegInit(State.IDLE)
val vpn1, vpn0 = Reg(UInt(10 bits))
val vpn = Reg(Vec(UInt(10 bits), UInt(10 bits)))
val portId = Reg(UInt(log2Up(portsInfo.length) bits))
case class PTE() extends Bundle {
val V, R, W ,X, U, G, A, D = Bool()
@ -160,8 +160,8 @@ class MmuPlugin(virtualRange : UInt => Bool,
for(port <- portsInfo.sortBy(_.priority)){
when(port.bus.cmd.isValid && port.bus.rsp.refilling){
busy := True
vpn1 := port.bus.cmd.virtualAddress(31 downto 22)
vpn0 := port.bus.cmd.virtualAddress(21 downto 12)
vpn(1) := port.bus.cmd.virtualAddress(31 downto 22)
vpn(0) := port.bus.cmd.virtualAddress(21 downto 12)
portId := port.id
state := State.L1_CMD
}
@ -169,7 +169,7 @@ class MmuPlugin(virtualRange : UInt => Bool,
}
is(State.L1_CMD){
dBusAccess.cmd.valid := True
dBusAccess.cmd.address := satp.ppn @@ vpn1 @@ U"00"
dBusAccess.cmd.address := satp.ppn @@ vpn(1) @@ U"00"
when(dBusAccess.cmd.ready){
state := State.L1_RSP
}
@ -185,7 +185,7 @@ class MmuPlugin(virtualRange : UInt => Bool,
}
is(State.L0_CMD){
dBusAccess.cmd.valid := True
dBusAccess.cmd.address := pteBuffer.PPN1(9 downto 0) @@ pteBuffer.PPN0 @@ vpn0 @@ U"00"
dBusAccess.cmd.address := pteBuffer.PPN1(9 downto 0) @@ pteBuffer.PPN0 @@ vpn(0) @@ U"00"
when(dBusAccess.cmd.ready){
state := State.L0_RSP
}
@ -203,14 +203,16 @@ class MmuPlugin(virtualRange : UInt => Bool,
port.entryToReplace.increment()
for ((line, lineId) <- port.cache.zipWithIndex) {
when(port.entryToReplace === lineId){
val superPage = state === State.L1_RSP
line.valid := True
line.exception := dBusRsp.exception
line.virtualAddress := vpn1 @@ vpn0
line.physicalAddress := dBusRsp.pte.PPN1(9 downto 0) @@ dBusRsp.pte.PPN0
line.exception := dBusRsp.exception || (superPage && dBusRsp.pte.PPN0 =/= 0)
line.virtualAddress := vpn
line.physicalAddress := Vec(dBusRsp.pte.PPN0, dBusRsp.pte.PPN1(9 downto 0))
line.allowRead := dBusRsp.pte.R
line.allowWrite := dBusRsp.pte.W
line.allowExecute := dBusRsp.pte.X
line.allowUser := dBusRsp.pte.U
line.superPage := state === State.L1_RSP
}
}
}

2
src/test/cpp/raw/common/asm.mk
View file

@ -27,7 +27,7 @@ OBJS := $(addprefix $(OBJDIR)/,$(OBJS))
all: $(OBJDIR)/$(PROJ_NAME).elf $(OBJDIR)/$(PROJ_NAME).hex $(OBJDIR)/$(PROJ_NAME).asm $(OBJDIR)/$(PROJ_NAME).v
all: $(OBJDIR)/$(PROJ_NAME).elf $(OBJDIR)/$(PROJ_NAME).hex $(OBJDIR)/$(PROJ_NAME).asm
@echo "done"
$(OBJDIR)/%.elf: $(OBJS) | $(OBJDIR)

178
src/test/cpp/raw/mmu/build/mmu.asm
View file

@ -4,7 +4,7 @@ build/mmu.elf: file format elf32-littleriscv
Disassembly of section .crt_section:
80000000 <trap_entry-0x20>:
80000000 <ROM_SUPER_0>:
80000000: 0280006f j 80000028 <_start>
80000004: 00000013 nop
80000008: 00000013 nop
@ -15,12 +15,12 @@ Disassembly of section .crt_section:
8000001c: 00000013 nop
80000020 <trap_entry>:
80000020: 1440006f j 80000164 <fail>
80000020: 1f80006f j 80000218 <fail>
80000024: 30200073 mret
80000028 <_start>:
80000028: 00000097 auipc ra,0x0
8000002c: 13c08093 addi ra,ra,316 # 80000164 <fail>
8000002c: 1f008093 addi ra,ra,496 # 80000218 <fail>
80000030: 30509073 csrw mtvec,ra
80000034: 10509073 csrw stvec,ra
@ -29,9 +29,9 @@ Disassembly of section .crt_section:
8000003c: 00007097 auipc ra,0x7
80000040: fc408093 addi ra,ra,-60 # 80007000 <ROM_2>
80000044: 27262137 lui sp,0x27262
80000048: 52410113 addi sp,sp,1316 # 27262524 <trap_entry-0x58d9dafc>
80000048: 52410113 addi sp,sp,1316 # 27262524 <ROM_SUPER_0-0x58d9dadc>
8000004c: 0040a083 lw ra,4(ra)
80000050: 10209a63 bne ra,sp,80000164 <fail>
80000050: 1c209463 bne ra,sp,80000218 <fail>
80000054 <test2>:
80000054: 00200e13 li t3,2
@ -39,30 +39,30 @@ Disassembly of section .crt_section:
8000005c: 02008093 addi ra,ra,32 # 80000078 <test3>
80000060: 34109073 csrw mepc,ra
80000064: 000020b7 lui ra,0x2
80000068: 80008093 addi ra,ra,-2048 # 1800 <trap_entry-0x7fffe820>
80000068: 80008093 addi ra,ra,-2048 # 1800 <ROM_SUPER_0-0x7fffe800>
8000006c: 30009073 csrw mstatus,ra
80000070: 30200073 mret
80000074: 0f00006f j 80000164 <fail>
80000074: 1a40006f j 80000218 <fail>
80000078 <test3>:
80000078: 00300e13 li t3,3
8000007c: 000010b7 lui ra,0x1
80000080: 80008093 addi ra,ra,-2048 # 800 <trap_entry-0x7ffff820>
80000080: 80008093 addi ra,ra,-2048 # 800 <ROM_SUPER_0-0x7ffff800>
80000084: 30009073 csrw mstatus,ra
80000088: 00000097 auipc ra,0x0
8000008c: 01408093 addi ra,ra,20 # 8000009c <test4>
80000090: 34109073 csrw mepc,ra
80000094: 30200073 mret
80000098: 0cc0006f j 80000164 <fail>
80000098: 1800006f j 80000218 <fail>
8000009c <test4>:
8000009c: 00400e13 li t3,4
800000a0: 00008097 auipc ra,0x8
800000a4: f6008093 addi ra,ra,-160 # 80008000 <ROM_3>
800000a8: 37363137 lui sp,0x37363
800000ac: 53410113 addi sp,sp,1332 # 37363534 <trap_entry-0x48c9caec>
800000ac: 53410113 addi sp,sp,1332 # 37363534 <ROM_SUPER_0-0x48c9cacc>
800000b0: 0040a083 lw ra,4(ra)
800000b4: 0a209863 bne ra,sp,80000164 <fail>
800000b4: 16209263 bne ra,sp,80000218 <fail>
800000b8 <test5>:
800000b8: 00500e13 li t3,5
@ -94,85 +94,93 @@ Disassembly of section .crt_section:
80000120: 00215113 srli sp,sp,0x2
80000124: 01f16113 ori sp,sp,31
80000128: 0020a023 sw sp,0(ra)
8000012c: 00001097 auipc ra,0x1
80000130: ed408093 addi ra,ra,-300 # 80001000 <MMU_TABLE_0>
80000134: 00c0d093 srli ra,ra,0xc
80000138: 80000137 lui sp,0x80000
8000013c: 0020e0b3 or ra,ra,sp
80000140: 18009073 csrw satp,ra
8000012c: 00500e13 li t3,5
80000130: 00002097 auipc ra,0x2
80000134: 8d008093 addi ra,ra,-1840 # 80001a00 <MMU_TABLE_0+0xa00>
80000138: 00000117 auipc sp,0x0
8000013c: ec810113 addi sp,sp,-312 # 80000000 <ROM_SUPER_0>
80000140: 00215113 srli sp,sp,0x2
80000144: 01f16113 ori sp,sp,31
80000148: 0020a023 sw sp,0(ra)
8000014c: 00001097 auipc ra,0x1
80000150: eb408093 addi ra,ra,-332 # 80001000 <MMU_TABLE_0>
80000154: 00c0d093 srli ra,ra,0xc
80000158: 80000137 lui sp,0x80000
8000015c: 0020e0b3 or ra,ra,sp
80000160: 18009073 csrw satp,ra
80000144 <test6>:
80000144: 00600e13 li t3,6
80000148: 9000a0b7 lui ra,0x9000a
8000014c: 00808093 addi ra,ra,8 # 9000a008 <ROM_7+0xfffe008>
80000150: 4b4a5137 lui sp,0x4b4a5
80000154: 94810113 addi sp,sp,-1720 # 4b4a4948 <trap_entry-0x34b5b6d8>
80000158: 0000a083 lw ra,0(ra)
8000015c: 00209463 bne ra,sp,80000164 <fail>
80000160: 0180006f j 80000178 <pass>
80000164 <test6>:
80000164: 00600e13 li t3,6
80000168: 9000a0b7 lui ra,0x9000a
8000016c: 00808093 addi ra,ra,8 # 9000a008 <ROM_7+0xfffe008>
80000170: 4b4a5137 lui sp,0x4b4a5
80000174: 94810113 addi sp,sp,-1720 # 4b4a4948 <ROM_SUPER_0-0x34b5b6b8>
80000178: 0000a083 lw ra,0(ra)
8000017c: 08209e63 bne ra,sp,80000218 <fail>
80000164 <fail>:
80000164: 18005073 csrwi satp,0
80000168: 0040006f j 8000016c <failFence>
80000180 <test7>:
80000180: 00700e13 li t3,7
80000184: 9000a0b7 lui ra,0x9000a
80000188: 36008093 addi ra,ra,864 # 9000a360 <ROM_7+0xfffe360>
8000018c: aaee0137 lui sp,0xaaee0
80000190: 00110113 addi sp,sp,1 # aaee0001 <ROM_7+0x2aed4001>
80000194: 0020a023 sw sp,0(ra)
80000198: 0000a083 lw ra,0(ra)
8000019c: 06209e63 bne ra,sp,80000218 <fail>
8000016c <failFence>:
8000016c: f0100137 lui sp,0xf0100
80000170: f2410113 addi sp,sp,-220 # f00fff24 <ROM_7+0x700f3f24>
80000174: 01c12023 sw t3,0(sp)
800001a0 <test8>:
800001a0: 00800e13 li t3,8
800001a4: 2000c097 auipc ra,0x2000c
800001a8: e6008093 addi ra,ra,-416 # a000c004 <ROM_7+0x20000004>
800001ac: 77767137 lui sp,0x77767
800001b0: 57410113 addi sp,sp,1396 # 77767574 <ROM_SUPER_0-0x8898a8c>
800001b4: 0000a083 lw ra,0(ra)
800001b8: 06209063 bne ra,sp,80000218 <fail>
80000178 <pass>:
80000178: 18005073 csrwi satp,0
8000017c: 0040006f j 80000180 <passFence>
800001bc <test9>:
800001bc: 00900e13 li t3,9
800001c0: a000a0b7 lui ra,0xa000a
800001c4: 36008093 addi ra,ra,864 # a000a360 <ROM_7+0x1fffe360>
800001c8: aaee0137 lui sp,0xaaee0
800001cc: 00210113 addi sp,sp,2 # aaee0002 <ROM_7+0x2aed4002>
800001d0: 0020a023 sw sp,0(ra)
800001d4: 0000a083 lw ra,0(ra)
800001d8: 04209063 bne ra,sp,80000218 <fail>
80000180 <passFence>:
80000180: f0100137 lui sp,0xf0100
80000184: f2010113 addi sp,sp,-224 # f00fff20 <ROM_7+0x700f3f20>
80000188: 00012023 sw zero,0(sp)
8000018c: 00000013 nop
80000190: 00000013 nop
80000194: 00000013 nop
80000198: 00000013 nop
8000019c: 00000013 nop
800001a0: 00000013 nop
800001a4: 00000013 nop
800001a8: 00000013 nop
800001ac: 00000013 nop
800001b0: 00000013 nop
800001b4: 00000013 nop
800001b8: 00000013 nop
800001bc: 00000013 nop
800001c0: 00000013 nop
800001c4: 00000013 nop
800001c8: 00000013 nop
800001cc: 00000013 nop
800001d0: 00000013 nop
800001d4: 00000013 nop
800001d8: 00000013 nop
800001dc: 00000013 nop
800001e0: 00000013 nop
800001e4: 00000013 nop
800001e8: 00000013 nop
800001ec: 00000013 nop
800001f0: 00000013 nop
800001f4: 00000013 nop
800001f8: 00000013 nop
800001fc: 00000013 nop
80000200: 00000013 nop
80000204: 00000013 nop
80000208: 00000013 nop
8000020c: 00000013 nop
80000210: 00000013 nop
80000214: 00000013 nop
80000218: 00000013 nop
8000021c: 00000013 nop
80000220: 00000013 nop
80000224: 00000013 nop
80000228: 00000013 nop
8000022c: 00000013 nop
80000230: 00000013 nop
80000234: 00000013 nop
80000238: 00000013 nop
8000023c: 00000013 nop
800001dc <test10>:
800001dc: 00a00e13 li t3,10
800001e0: 18005073 csrwi satp,0
800001e4: 00009097 auipc ra,0x9
800001e8: 17c08093 addi ra,ra,380 # 80009360 <ROM_4+0x360>
800001ec: aaee0137 lui sp,0xaaee0
800001f0: 00110113 addi sp,sp,1 # aaee0001 <ROM_7+0x2aed4001>
800001f4: 0000a083 lw ra,0(ra)
800001f8: 02209063 bne ra,sp,80000218 <fail>
800001fc: 0000a097 auipc ra,0xa
80000200: 16408093 addi ra,ra,356 # 8000a360 <ROM_5+0x360>
80000204: aaee0137 lui sp,0xaaee0
80000208: 00210113 addi sp,sp,2 # aaee0002 <ROM_7+0x2aed4002>
8000020c: 0000a083 lw ra,0(ra)
80000210: 00209463 bne ra,sp,80000218 <fail>
80000214: 0180006f j 8000022c <pass>
80000218 <fail>:
80000218: 18005073 csrwi satp,0
8000021c: 0040006f j 80000220 <failFence>
80000220 <failFence>:
80000220: f0100137 lui sp,0xf0100
80000224: f2410113 addi sp,sp,-220 # f00fff24 <ROM_7+0x700f3f24>
80000228: 01c12023 sw t3,0(sp)
8000022c <pass>:
8000022c: 18005073 csrwi satp,0
80000230: 0040006f j 80000234 <passFence>
80000234 <passFence>:
80000234: f0100137 lui sp,0xf0100
80000238: f2010113 addi sp,sp,-224 # f00fff20 <ROM_7+0x700f3f20>
8000023c: 00012023 sw zero,0(sp)
80000240: 00000013 nop
80000244: 00000013 nop
80000248: 00000013 nop

59
src/test/cpp/raw/mmu/build/mmu.hex
View file

@ -1,40 +1,40 @@
:0200000480007A
:100000006F008002130000001300000013000000C6
:100010001300000013000000130000001300000094
:100020006F00401473002030970000009380C013CD
:100020006F00801F73002030970000009380001F36
:100030007390503073905010130E100097700000A2
:10004000938040FC372126271301415283A04000B2
:10005000639A2010130E2000970000009380000286
:100050006394201C130E2000970000009380000280
:1000600073901034B72000009380008073900030AC
:10007000730020306F00000F130E3000B710000027
:10007000730020306F00401A130E3000B7100000DC
:1000800093800080739000309700000093804001BF
:1000900073901034730020306F00C00C130E4000BA
:1000900073901034730020306F000018130E40006E
:1000A00097800000938000F63731363713014153B3
:1000B00083A040006398200A130E500097100000A0
:1000B00083A0400063922016130E5000971000009A
:1000C00093804074172100001301C1F313512100E4
:1000D0001361110123A0200097200000938080F27B
:1000E00037010080135121001361F10123A020008A
:1000F000130E5000972000009380C080173100003D
:10010000130141F0135121001361110123A02000BC
:1001100097300000938080F117910000130181EE69
:10012000135121001361F10123A02000971000005A
:10013000938040ED93D0C00037010080B3E02000F1
:1001400073900018130E6000B7A000909380800099
:1001500037514A4B1301819483A00000639420001F
:100160006F008001735000186F004000370110F0DD
:10017000130141F22320C101735000186F004000A9
:10018000370110F0130101F22320010013000000D9
:100190001300000013000000130000001300000013
:1001A0001300000013000000130000001300000003
:1001B00013000000130000001300000013000000F3
:1001C00013000000130000001300000013000000E3
:1001D00013000000130000001300000013000000D3
:1001E00013000000130000001300000013000000C3
:1001F00013000000130000001300000013000000B3
:1002000013000000130000001300000013000000A2
:100210001300000013000000130000001300000092
:100220001300000013000000130000001300000082
:100230001300000013000000130000001300000072
:10012000135121001361F10123A02000130E500090
:10013000972000009380008D17010000130181ECCF
:10014000135121001361F10123A02000971000003A
:10015000938040EB93D0C00037010080B3E02000D3
:1001600073900018130E6000B7A000909380800079
:1001700037514A4B1301819483A00000639E2008ED
:10018000130E7000B7A00090938000363701EEAADE
:100190001301110023A0200083A00000639E20060D
:1001A000130E800097C00020938000E637717677A9
:1001B0001301415783A0000063902006130E9000A6
:1001C000B7A000A0938000363701EEAA13012100EA
:1001D00023A0200083A0000063902004130EA00041
:1001E00073500018979000009380C0173701EEAA53
:1001F0001301110083A000006390200297A000006B
:10020000938040163701EEAA1301210083A000005D
:10021000639420006F008001735000186F0040004D
:10022000370110F0130141F22320C101735000186F
:100230006F004000370110F0130101F2232001008C
:100240001300000013000000130000001300000062
:100250001300000013000000130000001300000052
:100260001300000013000000130000001300000042
@ -3284,17 +3284,6 @@
:10CD20000000000000000000000000000000000003
:10CD300000000000000000000000000000000000F3
:10CD400000000000000000000000000000000000E3
:10CD500000000000000000000000000000000000D3
:10CD600000000000000000000000000000000000C3
:10CD700000000000000000000000000000000000B3
:10CD800000000000000000000000000000000000A3
:10CD90000000000000000000000000000000000093
:10CDA0000000000000000000000000000000000083
:10CDB0000000000000000000000000000000000073
:10CDC0000000000000000000000000000000000063
:10CDD0000000000000000000000000000000000053
:10CDE0000000000000000000000000000000000043
:10CDF0000000000000000000000000000000000033
:0CCE000000000000000000000000000026
:08CD50000000000000000000DB
:04000005800000284F
:00000001FF

69
src/test/cpp/raw/mmu/src/crt.S
View file

@ -1,5 +1,6 @@
.globl _start
ROM_SUPER_0:
j _start
nop
@ -84,6 +85,14 @@ test5: //setup MMU
ori x2, x2, 0x1F
sw x2, 0(x1)
li x28, 5
la x1, MMU_TABLE_0 + 0xA00
la x2, ROM_SUPER_0
srli x2, x2, 2
ori x2, x2, 0x1F
sw x2, 0(x1)
la x1, MMU_TABLE_0
srli x1, x1, 12
li x2, 0x80000000
@ -91,7 +100,7 @@ test5: //setup MMU
csrw satp, x1
test6: //read through MMU !
test6: //read through MMU
li x28, 6
li x1, 0x9000A008
li x2, 0x4B4A4948
@ -100,6 +109,49 @@ test6: //read through MMU !
test7: //write-read through MMU
li x28, 7
li x1, 0x9000A360
li x2, 0xAAEE0001
sw x2, 0(x1)
lw x1, 0(x1)
bne x1, x2, fail
test8: //read through MMU super page
li x28, 8
la x1, ROM_7 + 0x20000004
li x2, 0x77767574
lw x1, 0(x1)
bne x1, x2, fail
test9: //write-read through MMU super page
li x28, 9
li x1, 0xA000A360
li x2, 0xAAEE0002
sw x2, 0(x1)
lw x1, 0(x1)
bne x1, x2, fail
test10: //check previously written value without the MMU
li x28, 10
csrwi satp, 0
la x1, ROM_4 + 0x360
li x2, 0xAAEE0001
lw x1, 0(x1)
bne x1, x2, fail
la x1, ROM_SUPER_0 + 0xA360
li x2, 0xAAEE0002
lw x1, 0(x1)
bne x1, x2, fail
@ -206,4 +258,19 @@ ROM_7:
.word 0x7B7A7978
.word 0x7F7E7D7C
/*
.align 22
ROM_SUPER_0:
.word 0x83828180
.word 0x87868584
.word 0x8B8A8988
.word 0x8F8E8D8C
.align 12
ROM_SUPER_1:
.word 0x93929190
.word 0x97969594
.word 0x9B9A9998
.word 0x9F9E9D9C*/

2
src/test/cpp/raw/mmu/src/ld
View file

@ -1,7 +1,7 @@
OUTPUT_ARCH( "riscv" )
MEMORY {
onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 1M
onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 128K
}
SECTIONS

10
src/test/cpp/regression/main.cpp
View file

@ -324,6 +324,11 @@ public:
uint32_t _dummy : 5;
uint32_t ppn : 22;
};
struct __attribute__((packed)){
uint32_t _dummyX : 10;
uint32_t ppn0 : 10;
uint32_t ppn1 : 12;
};
};
@ -377,17 +382,20 @@ public:
Tlb tlb;
dRead((satp.ppn << 12) | ((v >> 22) << 2), 4, &tlb.raw);
if(!tlb.v) return true;
bool superPage = true;
if(!tlb.x && !tlb.r && !tlb.w){
dRead((tlb.ppn << 12) | (((v >> 12) & 0x3FF) << 2), 4, &tlb.raw);
if(!tlb.v) return true;
superPage = false;
}
if(!tlb.u && privilege == 0) return true;
if(superPage && tlb.ppn0 != 0) return true;
switch(kind){
case READ: if(!tlb.r) return true; break;
case WRITE: if(!tlb.w) return true; break;
case EXECUTE: if(!tlb.x) return true; break;
}
*p = (tlb.ppn << 12) | (v & 0xFFF);
*p = (tlb.ppn1 << 22) | (superPage ? v & 0x3FF000 : tlb.ppn0 << 12) | (v & 0xFFF);
}
return false;
}