Charles Papon
parent
26597f78cd
commit
2f384364d8
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@ -0,0 +1,533 @@
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package SpinalRiscv.Plugin
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import spinal.core._
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import spinal.lib._
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class DBusCachedPlugin {
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}
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case class DataCacheConfig( cacheSize : Int,
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bytePerLine : Int,
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wayCount : Int,
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addressWidth : Int,
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cpuDataWidth : Int,
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memDataWidth : Int){
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def burstSize = bytePerLine*8/memDataWidth
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val burstLength = bytePerLine/(memDataWidth/8)
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}
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object DataCacheCpuCmdKind extends SpinalEnum{
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val MEMORY,FLUSH,EVICT = newElement()
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}
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object DataCacheCpuExecute{
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implicit def implArgs(that : DataCacheCpuExecute) = that.args
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}
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case class DataCacheCpuExecute(p : DataCacheConfig) extends Bundle with IMasterSlave{
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val isValid = Bool
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val isStuck = Bool
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val haltIt = Bool
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val args = DataCacheCpuExecuteArgs(p)
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override def asMaster(): Unit = {
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out(isValid, isStuck, args)
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in(haltIt)
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}
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}
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case class DataCacheCpuExecuteArgs(p : DataCacheConfig) extends Bundle{
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val kind = DataCacheCpuCmdKind()
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val wr = Bool
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val address = UInt(p.addressWidth bit)
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val data = Bits(p.cpuDataWidth bit)
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val mask = Bits(p.cpuDataWidth/8 bit)
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val bypass = Bool
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val all = Bool //Address should be zero when "all" is used
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}
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case class DataCacheCpuMemory(p : DataCacheConfig) extends Bundle with IMasterSlave{
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val isValid = Bool
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val isStall = Bool
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val haltIt = Bool
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override def asMaster(): Unit = {
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out(isValid, isStall)
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in(haltIt)
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}
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}
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case class DataCacheCpuWriteBack(p : DataCacheConfig) extends Bundle with IMasterSlave{
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val isValid = Bool
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val haltIt = Bool
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val data = Bits(p.cpuDataWidth bit)
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override def asMaster(): Unit = {
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out(isValid)
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in(haltIt, data)
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}
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}
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case class DataCacheCpuBus(p : DataCacheConfig) extends Bundle with IMasterSlave{
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val execute = DataCacheCpuExecute(p)
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val memory = DataCacheCpuMemory(p)
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val writeBack = DataCacheCpuWriteBack(p)
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override def asMaster(): Unit = {
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master(execute)
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master(memory)
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master(writeBack)
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}
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}
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case class DataCacheMemCmd(p : DataCacheConfig) extends Bundle{
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val wr = Bool
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val address = UInt(p.addressWidth bit)
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val data = Bits(p.memDataWidth bits)
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val mask = Bits(p.memDataWidth/8 bits)
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val length = UInt(log2Up(p.burstLength+1) bit)
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}
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case class DataCacheMemRsp(p : DataCacheConfig) extends Bundle{
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val data = Bits(p.memDataWidth bit)
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}
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case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave{
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val cmd = Stream (DataCacheMemCmd(p))
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val rsp = Flow (DataCacheMemRsp(p))
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override def asMaster(): Unit = {
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master(cmd)
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slave(rsp)
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}
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}
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class DataCache(p : DataCacheConfig) extends Component{
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import p._
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assert(wayCount == 1)
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assert(cpuDataWidth == memDataWidth)
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val io = new Bundle{
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val cpu = slave(DataCacheCpuBus(p))
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val mem = master(DataCacheMemBus(p))
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val flushDone = out Bool //It pulse at the same time than the manager.request.fire
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}
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val haltCpu = False
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val lineWidth = bytePerLine*8
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val lineCount = cacheSize/bytePerLine
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val wordWidth = Math.max(memDataWidth,cpuDataWidth)
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val wordWidthLog2 = log2Up(wordWidth)
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val wordPerLine = lineWidth/wordWidth
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val bytePerWord = wordWidth/8
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val wayLineCount = lineCount/wayCount
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val wayLineLog2 = log2Up(wayLineCount)
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val wayWordCount = wayLineCount * wordPerLine
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val memTransactionPerLine = p.bytePerLine / (p.memDataWidth/8)
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val tagRange = addressWidth-1 downto log2Up(wayLineCount*bytePerLine)
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val lineRange = tagRange.low-1 downto log2Up(bytePerLine)
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val wordRange = log2Up(bytePerLine)-1 downto log2Up(bytePerWord)
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class LineInfo() extends Bundle{
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val used = Bool
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val dirty = Bool
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val address = UInt(tagRange.length bit)
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}
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val tagsReadCmd = UInt(log2Up(wayLineCount) bits)
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val tagsWriteCmd = Flow(new Bundle{
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val way = UInt(log2Up(wayCount) bits)
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val address = UInt(log2Up(wayLineCount) bits)
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val data = new LineInfo()
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})
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val tagsWriteLastCmd = RegNext(tagsWriteCmd)
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val dataReadCmd = UInt(log2Up(wayWordCount) bits)
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val dataWriteCmd = Flow(new Bundle{
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val way = UInt(log2Up(wayCount) bits)
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val address = UInt(log2Up(wayWordCount) bits)
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val data = Bits(wordWidth bits)
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val mask = Bits(wordWidth/8 bits)
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})
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tagsWriteCmd.valid := False
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tagsWriteCmd.payload.assignDontCare()
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dataWriteCmd.valid := False
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dataWriteCmd.payload.assignDontCare()
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io.mem.cmd.valid := False
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io.mem.cmd.payload.assignDontCare()
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val ways = Array.tabulate(wayCount)(id => new Area{
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val tags = Mem(new LineInfo(),wayLineCount)
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val data = Mem(Bits(wordWidth bit),wayWordCount)
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when(tagsWriteCmd.valid && tagsWriteCmd.way === id){
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tags(tagsWriteCmd.address) := tagsWriteCmd.data
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}
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when(dataWriteCmd.valid && dataWriteCmd.way === id){
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data.write(
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address = dataWriteCmd.address,
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data = dataWriteCmd.data,
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mask = dataWriteCmd.mask
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)
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}
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val dataReadRsp = data.readSync(dataReadCmd)
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})
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val dataReadedValue = Vec(id => RegNext(ways(id).dataReadRsp),ways.length)
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val victim = new Area{
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val requestIn = Stream(cloneable(new Bundle{
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val way = UInt(log2Up(wayCount) bits)
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val address = UInt(p.addressWidth bits)
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}))
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requestIn.valid := False
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requestIn.payload.assignDontCare()
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val request = requestIn.stage()
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request.ready := False
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val buffer = Mem(Bits(p.memDataWidth bits),memTransactionPerLine << 1) // << 1 because of cyclone II issue, should be removed //.add(new AttributeString("ramstyle","M4K"))
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//Send line read commands to fill the buffer
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val readLineCmdCounter = Reg(UInt(log2Up(memTransactionPerLine + 1) bits)) init(0)
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val dataReadCmdOccure = False
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val dataReadCmdOccureLast = RegNext(dataReadCmdOccure)
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when(request.valid && !readLineCmdCounter.msb){
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readLineCmdCounter := readLineCmdCounter + 1
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//dataReadCmd := request.address(lineRange.high downto wordRange.low) Done in the manager
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dataReadCmdOccure := True
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}
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//Fill the buffer with line read responses
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val readLineRspCounter = Reg(UInt(log2Up(memTransactionPerLine + 1) bits)) init(0)
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when(readLineCmdCounter >= 2 && !readLineRspCounter.msb && Delay(dataReadCmdOccure,2)){
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buffer(readLineRspCounter.resized) := dataReadedValue(request.way)
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readLineRspCounter := readLineRspCounter + 1
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}
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//Send buffer read commands
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val bufferReadCounter = Reg(UInt(log2Up(memTransactionPerLine + 1) bits)) init(0)
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val bufferReadStream = Stream(buffer.addressType)
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bufferReadStream.valid := readLineRspCounter > bufferReadCounter
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bufferReadStream.payload := bufferReadCounter.resized
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when(bufferReadStream.fire){
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bufferReadCounter := bufferReadCounter + 1
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}
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val bufferReaded = buffer.streamReadSync(bufferReadStream).stage
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bufferReaded.ready := False
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//Send memory writes from bufffer read responses
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val bufferReadedCounter = Reg(UInt(log2Up(memTransactionPerLine) bits)) init(0)
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val memCmdAlreadyUsed = False
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when(bufferReaded.valid) {
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io.mem.cmd.valid := True
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io.mem.cmd.wr := True
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io.mem.cmd.address := request.address(tagRange.high downto lineRange.low) @@ U(0,lineRange.low bit)
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io.mem.cmd.length := p.burstLength
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io.mem.cmd.data := bufferReaded.payload
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io.mem.cmd.mask := (1<<(wordWidth/8))-1
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when(!memCmdAlreadyUsed && io.mem.cmd.ready){
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bufferReaded.ready := True
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bufferReadedCounter := bufferReadedCounter + 1
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when(bufferReadedCounter === bufferReadedCounter.maxValue){
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request.ready := True
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}
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}
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}
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val counter = Counter(memTransactionPerLine)
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when(request.ready){
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readLineCmdCounter.msb := False
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readLineRspCounter.msb := False
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bufferReadCounter.msb := False
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}
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}
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val manager = new Area {
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io.flushDone := False
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io.cpu.execute.haltIt := False
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val request = RegNextWhen(io.cpu.execute.args, !io.cpu.execute.isStuck)
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//Evict the cache after reset
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val requestValid = io.cpu.memory.isValid || RegNextWhen(False, !io.cpu.memory.isStall, True)
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request.kind.getDrivingReg.init(DataCacheCpuCmdKind.EVICT)
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request.all.getDrivingReg.init(True)
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request.address.getDrivingReg.init(0)
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io.cpu.memory.haltIt := requestValid
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val waysHitValid = False
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val waysHitOneHot = Bits(wayCount bits)
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val waysHitId = OHToUInt(waysHitOneHot)
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val waysHitInfo = new LineInfo().assignDontCare()
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//delayedXX are used to relax logic timings in flush and evict modes
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val delayedValid = RegNext(io.cpu.memory.isStall) init(False)
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val delayedWaysHitValid = RegNext(waysHitValid)
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val delayedWaysHitId = RegNext(waysHitId)
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val waysReadAddress = Mux(io.cpu.memory.isStall, request.address, io.cpu.execute.address)
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tagsReadCmd := waysReadAddress(lineRange)
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dataReadCmd := waysReadAddress(lineRange.high downto wordRange.low)
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when(victim.dataReadCmdOccure){
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dataReadCmd := victim.request.address(lineRange) @@ victim.readLineCmdCounter(victim.readLineCmdCounter.high-1 downto 0)
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}
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val waysRead = for ((way,id) <- ways.zipWithIndex) yield new Area {
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val tag = way.tags.readSync(tagsReadCmd)
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//Write first
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when(tagsWriteLastCmd.valid && tagsWriteLastCmd.way === id && tagsWriteLastCmd.address === RegNext(waysReadAddress(lineRange))){
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tag := tagsWriteLastCmd.data
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}
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waysHitOneHot(id) := tag.used && tag.address === request.address(tagRange)
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when(waysHitOneHot(id)) {
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waysHitValid := True
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waysHitInfo := tag
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}
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}
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val writebackWayId = U(0) //Only one way compatible
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val writebackWayInfo = Vec(waysRead.map(_.tag))(writebackWayId)
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val cpuRspIn = Stream(wrap(new Bundle{
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val fromBypass = Bool
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val wayId = UInt(log2Up(wayCount) bits)
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}))
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cpuRspIn.valid := False
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cpuRspIn.fromBypass := False
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cpuRspIn.wayId := waysHitId
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//Loader interface
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val loaderValid = False
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val loaderReady = False
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val loadingDone = RegNext(loaderValid && loaderReady) init(False) //one cycle pulse
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val victimSent = RegInit(False)
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victimSent := (victimSent || victim.requestIn.fire) && io.cpu.memory.isStall
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val flushAllState = RegInit(False) //Used to keep logic timings fast
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val flushAllDone = RegNext(False) init(False)
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when(requestValid) {
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switch(request.kind) {
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import DataCacheCpuCmdKind._
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is(EVICT){
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when(request.all){
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tagsWriteCmd.valid := True
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tagsWriteCmd.way := 0
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tagsWriteCmd.address := request.address(lineRange)
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tagsWriteCmd.data.used := False
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when(request.address(lineRange) =/= lineCount-1){
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request.address.getDrivingReg(lineRange) := request.address(lineRange) + 1
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}otherwise{
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io.cpu.memory.haltIt := False
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}
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}otherwise{
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when(delayedValid) {
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when(delayedWaysHitValid) {
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tagsWriteCmd.valid := True
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tagsWriteCmd.way := delayedWaysHitId
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tagsWriteCmd.address := request.address(lineRange)
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tagsWriteCmd.data.used := False
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}
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io.cpu.memory.haltIt := False
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}
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}
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}
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is(FLUSH) {
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when(request.all) {
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when(!flushAllState){
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victim.requestIn.valid := waysRead(0).tag.used && waysRead(0).tag.dirty
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victim.requestIn.way := writebackWayId
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victim.requestIn.address := writebackWayInfo.address @@ request.address(lineRange) @@ U((lineRange.low - 1 downto 0) -> false)
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tagsWriteCmd.way := writebackWayId
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tagsWriteCmd.address := request.address(lineRange)
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tagsWriteCmd.data.used := False
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when(!victim.requestIn.isStall) {
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request.address.getDrivingReg(lineRange) := request.address(lineRange) + 1
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flushAllDone := request.address(lineRange) === lineCount-1
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flushAllState := True
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tagsWriteCmd.valid := True
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}
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} otherwise{
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//Wait tag read
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flushAllState := False
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io.cpu.memory.haltIt.clearWhen(flushAllDone)
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io.flushDone := flushAllDone
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}
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} otherwise {
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when(delayedValid) {
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when(delayedWaysHitValid) {
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io.cpu.memory.haltIt.clearWhen(victim.requestIn.ready)
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victim.requestIn.valid := True
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victim.requestIn.way := writebackWayId
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victim.requestIn.address := writebackWayInfo.address @@ request.address(lineRange) @@ U((lineRange.low - 1 downto 0) -> false)
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tagsWriteCmd.valid := victim.requestIn.ready
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tagsWriteCmd.way := writebackWayId
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tagsWriteCmd.address := request.address(lineRange)
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tagsWriteCmd.data.used := False
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} otherwise{
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io.cpu.memory.haltIt := False
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io.flushDone := True
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}
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}
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}
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}
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is(MEMORY) {
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when(request.bypass) {
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when(!victim.request.valid) {
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//Can't insert mem cmd into a victim write burst
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io.mem.cmd.valid := !(!request.wr && !cpuRspIn.ready)
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io.mem.cmd.wr := request.wr
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io.mem.cmd.address := request.address(tagRange.high downto wordRange.low) @@ U(0,wordRange.low bit)
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io.mem.cmd.mask := request.mask
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io.mem.cmd.data := request.data
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io.mem.cmd.length := 1
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cpuRspIn.valid := !request.wr && io.mem.cmd.fire
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cpuRspIn.fromBypass := True
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io.cpu.memory.haltIt.clearWhen(io.mem.cmd.fire)
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} otherwise {
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io.cpu.memory.haltIt := True //TODO redondent ?
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}
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} otherwise {
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when(waysHitValid && !loadingDone) { // !loadingDone => don't solve the request directly after loader (data write to read latency)
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when(request.wr) {
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dataWriteCmd.valid := True
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dataWriteCmd.way := waysHitId
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dataWriteCmd.address := request.address(lineRange.high downto wordRange.low)
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dataWriteCmd.data := request.data
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dataWriteCmd.mask := request.mask
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tagsWriteCmd.valid := True
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tagsWriteCmd.way := waysHitId
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tagsWriteCmd.address := request.address(lineRange)
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tagsWriteCmd.data.used := True
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tagsWriteCmd.data.dirty := True
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tagsWriteCmd.data.address := request.address(tagRange)
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io.cpu.memory.haltIt := False
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} otherwise {
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cpuRspIn.valid := !victim.dataReadCmdOccureLast
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io.cpu.memory.haltIt.clearWhen(cpuRspIn.ready && !victim.dataReadCmdOccureLast) //dataReadCmdOccure to avoid the case where flush,then read will victim use data read
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}
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} otherwise {
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io.cpu.memory.haltIt := True //Exit this state automaticly (tags read port write first logic) TODO redondent ?
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loaderValid := !loadingDone && !(!victimSent && victim.request.isStall) //Wait previous victim request to be completed
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when(writebackWayInfo.used && writebackWayInfo.dirty) {
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victim.requestIn.valid := !victimSent
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victim.requestIn.way := writebackWayId
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victim.requestIn.address := writebackWayInfo.address @@ request.address(lineRange) @@ U((lineRange.low - 1 downto 0) -> false)
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}
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}
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}
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}
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}
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}
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val cpuRsp = cpuRspIn.m2sPipe()
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val cpuRspIsWaitingMemRsp = cpuRsp.valid && io.mem.rsp.valid
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io.cpu.writeBack.haltIt := io.cpu.memory.isValid && cpuRsp.isStall
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io.cpu.writeBack.data := Mux(cpuRsp.fromBypass,io.mem.rsp.data,dataReadedValue(cpuRsp.wayId))
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cpuRsp.ready := !(cpuRsp.fromBypass && !io.mem.rsp.valid)
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}
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//The whole life of a loading task, the corresponding manager request is present
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val loader = new Area{
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val valid = RegNext(manager.loaderValid)
|
||||
val wayId = RegNext(manager.writebackWayId)
|
||||
val baseAddress = manager.request.address
|
||||
|
||||
val memCmdSent = RegInit(False)
|
||||
when(valid && !memCmdSent) {
|
||||
io.mem.cmd.valid := True
|
||||
io.mem.cmd.wr := False
|
||||
io.mem.cmd.address := baseAddress(tagRange.high downto lineRange.low) @@ U(0,lineRange.low bit)
|
||||
io.mem.cmd.length := p.burstLength
|
||||
}
|
||||
|
||||
when(valid && io.mem.cmd.ready){
|
||||
memCmdSent := True
|
||||
}
|
||||
|
||||
when(valid && !memCmdSent) {
|
||||
victim.memCmdAlreadyUsed := True
|
||||
}
|
||||
|
||||
val counter = Counter(memTransactionPerLine)
|
||||
when(io.mem.rsp.valid && !manager.cpuRspIsWaitingMemRsp){
|
||||
dataWriteCmd.valid := True
|
||||
dataWriteCmd.way := wayId
|
||||
dataWriteCmd.address := baseAddress(lineRange) @@ counter
|
||||
dataWriteCmd.data := io.mem.rsp.data
|
||||
dataWriteCmd.mask := (1<<(wordWidth/8))-1
|
||||
counter.increment()
|
||||
}
|
||||
|
||||
when(counter.willOverflow){
|
||||
memCmdSent := False
|
||||
valid := False
|
||||
tagsWriteCmd.valid := True
|
||||
tagsWriteCmd.way := wayId
|
||||
tagsWriteCmd.address := baseAddress(lineRange)
|
||||
tagsWriteCmd.data.used := True
|
||||
tagsWriteCmd.data.dirty := False
|
||||
tagsWriteCmd.data.address := baseAddress(tagRange)
|
||||
manager.loaderReady := True
|
||||
}
|
||||
}
|
||||
|
||||
//Avoid read after write data hazard
|
||||
//TODO FIX it to not stall write after read ? , requestValid is pessimistic ?
|
||||
io.cpu.execute.haltIt := io.cpu.execute.address === manager.request.address && manager.requestValid && io.cpu.execute.isValid
|
||||
}
|
||||
|
||||
object DataCacheMain{
|
||||
def main(args: Array[String]) {
|
||||
|
||||
SpinalVhdl({
|
||||
implicit val p = DataCacheConfig(
|
||||
cacheSize =4096,
|
||||
bytePerLine =32,
|
||||
wayCount = 1,
|
||||
addressWidth = 32,
|
||||
cpuDataWidth = 32,
|
||||
memDataWidth = 32)
|
||||
new WrapWithReg.Wrapper(new DataCache(p)).setDefinitionName("TopLevel")
|
||||
})
|
||||
// SpinalVhdl({
|
||||
// implicit val p = DataCacheConfig(
|
||||
// cacheSize =512,
|
||||
// bytePerLine =16,
|
||||
// wayCount = 1,
|
||||
// addressWidth = 12,
|
||||
// cpuDataWidth = 16,
|
||||
// memDataWidth = 16)
|
||||
// new DataCache(p)
|
||||
// })
|
||||
}
|
||||
}
|
||||
|
|
@ -12,16 +12,29 @@ case class DBusSimpleCmd() extends Bundle{
|
|||
val size = UInt(2 bit)
|
||||
}
|
||||
|
||||
case class DBusSimpleRsp() extends Bundle{
|
||||
case class DBusSimpleRsp() extends Bundle with IMasterSlave{
|
||||
val ready = Bool
|
||||
val error = Bool
|
||||
val data = Bits(32 bit)
|
||||
|
||||
override def asMaster(): Unit = {
|
||||
out(ready,error,data)
|
||||
}
|
||||
}
|
||||
|
||||
case class DBusSimpleBus() extends Bundle with IMasterSlave{
|
||||
val cmd = Stream(DBusSimpleCmd())
|
||||
val rsp = DBusSimpleRsp()
|
||||
|
||||
override def asMaster(): Unit = {
|
||||
master(cmd)
|
||||
slave(rsp)
|
||||
}
|
||||
}
|
||||
|
||||
class DBusSimplePlugin(catchAddressMisaligned : Boolean, catchAccessFault : Boolean) extends Plugin[VexRiscv]{
|
||||
|
||||
var dCmd : Stream[DBusSimpleCmd] = null
|
||||
var dRsp : DBusSimpleRsp = null
|
||||
var dBus : DBusSimpleBus = null
|
||||
|
||||
object MemoryCtrlEnum extends SpinalEnum{
|
||||
val WR, RD = newElement()
|
||||
|
|
@ -88,49 +101,50 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean, catchAccessFault : Bool
|
|||
import pipeline._
|
||||
import pipeline.config._
|
||||
|
||||
//Emit dCmd request
|
||||
dBus = master(DBusSimpleBus()).setName("dBus")
|
||||
|
||||
//Emit dBus.cmd request
|
||||
execute plug new Area{
|
||||
import execute._
|
||||
|
||||
dCmd = master(Stream(DBusSimpleCmd())).setName("dCmd")
|
||||
dCmd.valid := arbitration.isValid && input(MEMORY_ENABLE) && !arbitration.isStuckByOthers && !arbitration.removeIt
|
||||
dCmd.wr := input(INSTRUCTION)(5)
|
||||
dCmd.address := input(SRC_ADD_SUB).asUInt
|
||||
dCmd.size := input(INSTRUCTION)(13 downto 12).asUInt
|
||||
dCmd.payload.data := dCmd.size.mux (
|
||||
dBus.cmd.valid := arbitration.isValid && input(MEMORY_ENABLE) && !arbitration.isStuckByOthers && !arbitration.removeIt
|
||||
dBus.cmd.wr := input(INSTRUCTION)(5)
|
||||
dBus.cmd.address := input(SRC_ADD_SUB).asUInt
|
||||
dBus.cmd.size := input(INSTRUCTION)(13 downto 12).asUInt
|
||||
dBus.cmd.payload.data := dBus.cmd.size.mux (
|
||||
U(0) -> input(REG2)(7 downto 0) ## input(REG2)(7 downto 0) ## input(REG2)(7 downto 0) ## input(REG2)(7 downto 0),
|
||||
U(1) -> input(REG2)(15 downto 0) ## input(REG2)(15 downto 0),
|
||||
default -> input(REG2)(31 downto 0)
|
||||
)
|
||||
when(arbitration.isValid && input(MEMORY_ENABLE) && !dCmd.ready){
|
||||
when(arbitration.isValid && input(MEMORY_ENABLE) && !dBus.cmd.ready){
|
||||
arbitration.haltIt := True
|
||||
}
|
||||
|
||||
insert(MEMORY_ADDRESS_LOW) := dCmd.address(1 downto 0)
|
||||
insert(MEMORY_ADDRESS_LOW) := dBus.cmd.address(1 downto 0)
|
||||
|
||||
if(catchAddressMisaligned){
|
||||
executeExceptionPort.code := (dCmd.wr ? U(6) | U(4)).resized
|
||||
executeExceptionPort.badAddr := dCmd.address
|
||||
executeExceptionPort.code := (dBus.cmd.wr ? U(6) | U(4)).resized
|
||||
executeExceptionPort.badAddr := dBus.cmd.address
|
||||
executeExceptionPort.valid := (arbitration.isValid && input(MEMORY_ENABLE)
|
||||
&& ((dCmd.size === 2 && dCmd.address(1 downto 0) =/= 0) || (dCmd.size === 1 && dCmd.address(0 downto 0) =/= 0)))
|
||||
&& ((dBus.cmd.size === 2 && dBus.cmd.address(1 downto 0) =/= 0) || (dBus.cmd.size === 1 && dBus.cmd.address(0 downto 0) =/= 0)))
|
||||
}
|
||||
}
|
||||
|
||||
//Collect dRsp read responses
|
||||
//Collect dBus.rsp read responses
|
||||
memory plug new Area {
|
||||
import memory._
|
||||
|
||||
dRsp = in(DBusSimpleRsp()).setName("dRsp")
|
||||
insert(MEMORY_READ_DATA) := dRsp.data
|
||||
arbitration.haltIt setWhen(arbitration.isValid && input(MEMORY_ENABLE) && !dRsp.ready)
|
||||
|
||||
insert(MEMORY_READ_DATA) := dBus.rsp.data
|
||||
arbitration.haltIt setWhen(arbitration.isValid && input(MEMORY_ENABLE) && !dBus.rsp.ready)
|
||||
|
||||
if(catchAccessFault){
|
||||
memoryExceptionPort.valid := arbitration.isValid && input(MEMORY_ENABLE) && dRsp.ready && dRsp.error
|
||||
memoryExceptionPort.valid := arbitration.isValid && input(MEMORY_ENABLE) && dBus.rsp.ready && dBus.rsp.error
|
||||
memoryExceptionPort.code := 5
|
||||
memoryExceptionPort.badAddr := input(REGFILE_WRITE_DATA).asUInt //Drived by IntAluPlugin
|
||||
}
|
||||
|
||||
assert(!(dRsp.ready && input(MEMORY_ENABLE) && arbitration.isValid && arbitration.isStuck),"DBusSimplePlugin doesn't allow memory stage stall when read happend")
|
||||
assert(!(dBus.rsp.ready && input(MEMORY_ENABLE) && arbitration.isValid && arbitration.isStuck),"DBusSimplePlugin doesn't allow memory stage stall when read happend")
|
||||
}
|
||||
|
||||
//Reformat read responses, REGFILE_WRITE_DATA overriding
|
||||
|
|
|
|||
|
|
@ -9,15 +9,29 @@ case class IBusSimpleCmd() extends Bundle{
|
|||
val pc = UInt(32 bits)
|
||||
}
|
||||
|
||||
case class IBusSimpleRsp() extends Bundle{
|
||||
case class IBusSimpleRsp() extends Bundle with IMasterSlave{
|
||||
val ready = Bool
|
||||
val error = Bool
|
||||
val inst = Bits(32 bits)
|
||||
|
||||
override def asMaster(): Unit = {
|
||||
out(ready,error,inst)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
case class IBusSimpleBus() extends Bundle with IMasterSlave{
|
||||
var cmd = Stream(IBusSimpleCmd())
|
||||
var rsp = IBusSimpleRsp()
|
||||
|
||||
override def asMaster(): Unit = {
|
||||
master(cmd)
|
||||
slave(rsp)
|
||||
}
|
||||
}
|
||||
|
||||
class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean) extends Plugin[VexRiscv]{
|
||||
var iCmd : Stream[IBusSimpleCmd] = null
|
||||
var iRsp : IBusSimpleRsp = null
|
||||
var iBus : IBusSimpleBus = null
|
||||
|
||||
object IBUS_ACCESS_ERROR extends Stageable(Bool)
|
||||
var decodeExceptionPort : Flow[ExceptionCause] = null
|
||||
|
|
@ -34,18 +48,18 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean)
|
|||
import pipeline._
|
||||
import pipeline.config._
|
||||
|
||||
//Emit iCmd request
|
||||
require(interfaceKeepData)
|
||||
iCmd = master(Stream(IBusSimpleCmd())).setName("iCmd")
|
||||
iCmd.valid := prefetch.arbitration.isFiring //prefetch.arbitration.isValid && !prefetch.arbitration.isStuckByOthers
|
||||
iCmd.pc := prefetch.output(PC)
|
||||
prefetch.arbitration.haltIt setWhen(!iCmd.ready)
|
||||
iBus = master(IBusSimpleBus()).setName("iBus")
|
||||
|
||||
//Emit iBus.cmd request
|
||||
iBus.cmd.valid := prefetch.arbitration.isFiring //prefetch.arbitration.isValid && !prefetch.arbitration.isStuckByOthers
|
||||
iBus.cmd.pc := prefetch.output(PC)
|
||||
prefetch.arbitration.haltIt setWhen(!iBus.cmd.ready)
|
||||
|
||||
//Insert iRsp into INSTRUCTION
|
||||
iRsp = in(IBusSimpleRsp()).setName("iRsp")
|
||||
fetch.insert(INSTRUCTION) := iRsp.inst
|
||||
fetch.insert(IBUS_ACCESS_ERROR) := iRsp.error
|
||||
fetch.arbitration.haltIt setWhen(fetch.arbitration.isValid && !iRsp.ready)
|
||||
//Insert iBus.rsp into INSTRUCTION
|
||||
fetch.insert(INSTRUCTION) := iBus.rsp.inst
|
||||
fetch.insert(IBUS_ACCESS_ERROR) := iBus.rsp.error
|
||||
fetch.arbitration.haltIt setWhen(fetch.arbitration.isValid && !iBus.rsp.ready)
|
||||
|
||||
if(catchAccessFault){
|
||||
decodeExceptionPort.valid := decode.arbitration.isValid && decode.input(IBUS_ACCESS_ERROR)
|
||||
|
|
|
|||
|
|
@ -79,22 +79,22 @@ object TopLevel {
|
|||
|
||||
config.plugins ++= List(
|
||||
new PcManagerSimplePlugin(0x00000000l, false),
|
||||
// new IBusSimplePlugin(
|
||||
// interfaceKeepData = true,
|
||||
// catchAccessFault = true
|
||||
// ),
|
||||
new IBusCachedPlugin(
|
||||
config = InstructionCacheConfig(
|
||||
cacheSize =4096,
|
||||
bytePerLine =32,
|
||||
wayCount = 1,
|
||||
wrappedMemAccess = true,
|
||||
addressWidth = 32,
|
||||
cpuDataWidth = 32,
|
||||
memDataWidth = 32,
|
||||
catchAccessFault = true
|
||||
)
|
||||
new IBusSimplePlugin(
|
||||
interfaceKeepData = true,
|
||||
catchAccessFault = true
|
||||
),
|
||||
// new IBusCachedPlugin(
|
||||
// config = InstructionCacheConfig(
|
||||
// cacheSize =4096,
|
||||
// bytePerLine =32,
|
||||
// wayCount = 1,
|
||||
// wrappedMemAccess = true,
|
||||
// addressWidth = 32,
|
||||
// cpuDataWidth = 32,
|
||||
// memDataWidth = 32,
|
||||
// catchAccessFault = true
|
||||
// )
|
||||
// ),
|
||||
new DecoderSimplePlugin(
|
||||
catchIllegalInstruction = true
|
||||
),
|
||||
|
|
|
|||
|
|
@ -141,8 +141,7 @@ public:
|
|||
};
|
||||
|
||||
|
||||
class Workspace;
|
||||
void fillSimELements(Workspace *ws);
|
||||
|
||||
|
||||
class Workspace{
|
||||
public:
|
||||
|
|
@ -150,6 +149,8 @@ public:
|
|||
vector<SimElement*> simElements;
|
||||
Memory mem;
|
||||
string name;
|
||||
uint64_t mTimeCmp = 0;
|
||||
uint64_t mTime = 0;
|
||||
VVexRiscv* top;
|
||||
int i;
|
||||
uint32_t bootPc = -1;
|
||||
|
|
@ -173,7 +174,7 @@ public:
|
|||
regTraces.open (name + ".regTrace");
|
||||
memTraces.open (name + ".memTrace");
|
||||
logTraces.open (name + ".logTrace");
|
||||
fillSimELements(this);
|
||||
fillSimELements();
|
||||
}
|
||||
|
||||
virtual ~Workspace(){
|
||||
|
|
@ -190,7 +191,7 @@ public:
|
|||
|
||||
Workspace* bootAt(uint32_t pc) { bootPc = pc;}
|
||||
|
||||
virtual bool isAccessError(uint32_t addr) { return addr == 0xF00FFF60u; }
|
||||
|
||||
virtual void iBusAccess(uint32_t addr, uint32_t *data, bool *error) {
|
||||
assert(addr % 4 == 0);
|
||||
*data = ( (mem[addr + 0] << 0)
|
||||
|
|
@ -199,10 +200,66 @@ public:
|
|||
| (mem[addr + 3] << 24));
|
||||
*error = addr == 0xF00FFF60u;
|
||||
}
|
||||
virtual void dBusAccess(uint32_t addr,bool wr, uint32_t size, uint32_t *data, bool *error) {
|
||||
*error = addr == 0xF00FFF60u;
|
||||
if(wr){
|
||||
memTraces <<
|
||||
#ifdef TRACE_WITH_TIME
|
||||
(currentTime
|
||||
#ifdef REF
|
||||
-2
|
||||
#endif
|
||||
) <<
|
||||
#endif
|
||||
" : WRITE mem" << (1 << size) << "[" << addr << "] = " << *data << endl;
|
||||
for(uint32_t b = 0;b < (1 << size);b++){
|
||||
uint32_t offset = (addr+b)&0x3;
|
||||
*mem.get(addr + b) = *data >> (offset*8);
|
||||
}
|
||||
|
||||
switch(addr){
|
||||
case 0xF00FFF00u: {
|
||||
cout << mem[0xF00FFF00u];
|
||||
logTraces << (char)mem[0xF00FFF00u];
|
||||
break;
|
||||
}
|
||||
case 0xF00FFF20u: pass(); break;
|
||||
case 0xF00FFF48u: mTimeCmp = (mTimeCmp & 0xFFFFFFFF00000000) | *data;break;
|
||||
case 0xF00FFF4Cu: mTimeCmp = (mTimeCmp & 0x00000000FFFFFFFF) | (((uint64_t)*data) << 32); /*cout << "mTimeCmp <= " << mTimeCmp << endl; */break;
|
||||
}
|
||||
}else{
|
||||
*data = VL_RANDOM_I(32);
|
||||
for(uint32_t b = 0;b < (1 << size);b++){
|
||||
uint32_t offset = (addr+b)&0x3;
|
||||
*data &= ~(0xFF << (offset*8));
|
||||
*data |= mem[addr + b] << (offset*8);
|
||||
}
|
||||
switch(addr){
|
||||
case 0xF00FFF10u:
|
||||
*data = i/2;
|
||||
break;
|
||||
case 0xF00FFF40u: *data = mTime; break;
|
||||
case 0xF00FFF44u: *data = mTime >> 32; break;
|
||||
case 0xF00FFF48u: *data = mTimeCmp; break;
|
||||
case 0xF00FFF4Cu: *data = mTimeCmp >> 32; break;
|
||||
}
|
||||
memTraces <<
|
||||
#ifdef TRACE_WITH_TIME
|
||||
(currentTime
|
||||
#ifdef REF
|
||||
-2
|
||||
#endif
|
||||
) <<
|
||||
#endif
|
||||
" : READ mem" << (1 << size) << "[" << addr << "] = " << *data << endl;
|
||||
|
||||
}
|
||||
}
|
||||
virtual void postReset() {}
|
||||
virtual void checks(){}
|
||||
virtual void pass(){ throw success();}
|
||||
virtual void fail(){ throw std::exception();}
|
||||
virtual void fillSimELements();
|
||||
void dump(int i){
|
||||
#ifdef TRACE
|
||||
if(i/2 >= TRACE_START) tfp->dump(i);
|
||||
|
|
@ -210,8 +267,7 @@ public:
|
|||
}
|
||||
Workspace* run(uint32_t timeout = 5000){
|
||||
// cout << "Start " << name << endl;
|
||||
uint64_t mTimeCmp = 0;
|
||||
uint64_t mTime = 0;
|
||||
|
||||
currentTime = 4;
|
||||
// init trace dump
|
||||
Verilated::traceEverOn(true);
|
||||
|
|
@ -224,8 +280,6 @@ public:
|
|||
// Reset
|
||||
top->clk = 0;
|
||||
top->reset = 0;
|
||||
top->dCmd_ready = 1;
|
||||
top->dRsp_ready = 1;
|
||||
|
||||
for(SimElement* simElement : simElements) simElement->onReset();
|
||||
|
||||
|
|
@ -251,9 +305,6 @@ public:
|
|||
|
||||
try {
|
||||
// run simulation for 100 clock periods
|
||||
uint32_t dRsp_inst_next = VL_RANDOM_I(32);
|
||||
bool dRsp_error_next = false;
|
||||
bool dRsp_ready_pending = false;
|
||||
for (i = 16; i < timeout*2; i+=2) {
|
||||
mTime = i/2;
|
||||
#ifdef CSR
|
||||
|
|
@ -275,63 +326,6 @@ public:
|
|||
dump(i + 1);
|
||||
|
||||
|
||||
if (top->dCmd_valid && top->dCmd_ready && ! dRsp_ready_pending) {
|
||||
dRsp_ready_pending = true;
|
||||
dRsp_inst_next = VL_RANDOM_I(32);
|
||||
uint32_t addr = top->dCmd_payload_address;
|
||||
dRsp_error_next = isAccessError(addr);
|
||||
if(top->dCmd_payload_wr){
|
||||
memTraces <<
|
||||
#ifdef TRACE_WITH_TIME
|
||||
(currentTime
|
||||
#ifdef REF
|
||||
-2
|
||||
#endif
|
||||
) <<
|
||||
#endif
|
||||
" : WRITE mem" << (1 << top->dCmd_payload_size) << "[" << addr << "] = " << top->dCmd_payload_data << endl;
|
||||
for(uint32_t b = 0;b < (1 << top->dCmd_payload_size);b++){
|
||||
uint32_t offset = (addr+b)&0x3;
|
||||
*mem.get(addr + b) = top->dCmd_payload_data >> (offset*8);
|
||||
}
|
||||
|
||||
switch(addr){
|
||||
case 0xF00FFF00u: {
|
||||
cout << mem[0xF00FFF00u];
|
||||
logTraces << (char)mem[0xF00FFF00u];
|
||||
break;
|
||||
}
|
||||
case 0xF00FFF20u: pass(); break;
|
||||
case 0xF00FFF48u: mTimeCmp = (mTimeCmp & 0xFFFFFFFF00000000) | top->dCmd_payload_data;break;
|
||||
case 0xF00FFF4Cu: mTimeCmp = (mTimeCmp & 0x00000000FFFFFFFF) | (((uint64_t)top->dCmd_payload_data) << 32); /*cout << "mTimeCmp <= " << mTimeCmp << endl; */break;
|
||||
}
|
||||
}else{
|
||||
for(uint32_t b = 0;b < (1 << top->dCmd_payload_size);b++){
|
||||
uint32_t offset = (addr+b)&0x3;
|
||||
dRsp_inst_next &= ~(0xFF << (offset*8));
|
||||
dRsp_inst_next |= mem[addr + b] << (offset*8);
|
||||
}
|
||||
switch(addr){
|
||||
case 0xF00FFF10u:
|
||||
dRsp_inst_next = i/2;
|
||||
break;
|
||||
case 0xF00FFF40u: dRsp_inst_next = mTime; break;
|
||||
case 0xF00FFF44u: dRsp_inst_next = mTime >> 32; break;
|
||||
case 0xF00FFF48u: dRsp_inst_next = mTimeCmp; break;
|
||||
case 0xF00FFF4Cu: dRsp_inst_next = mTimeCmp >> 32; break;
|
||||
}
|
||||
memTraces <<
|
||||
#ifdef TRACE_WITH_TIME
|
||||
(currentTime
|
||||
#ifdef REF
|
||||
-2
|
||||
#endif
|
||||
) <<
|
||||
#endif
|
||||
" : READ mem" << (1 << top->dCmd_payload_size) << "[" << addr << "] = " << dRsp_inst_next << endl;
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
if(top->VexRiscv->writeBack_RegFilePlugin_regFileWrite_valid == 1 && top->VexRiscv->writeBack_RegFilePlugin_regFileWrite_payload_address != 0){
|
||||
regTraces <<
|
||||
|
|
@ -358,17 +352,6 @@ public:
|
|||
|
||||
for(SimElement* simElement : simElements) simElement->postCycle();
|
||||
|
||||
top->dRsp_ready = 0;
|
||||
if(dRsp_ready_pending && (!dStall || VL_RANDOM_I(8) < 100)){
|
||||
top->dRsp_data = dRsp_inst_next;
|
||||
dRsp_ready_pending = false;
|
||||
top->dRsp_ready = 1;
|
||||
top->dRsp_error = dRsp_error_next;
|
||||
} else{
|
||||
top->dRsp_data = VL_RANDOM_I(32);
|
||||
}
|
||||
|
||||
if(dStall) top->dCmd_ready = VL_RANDOM_I(8) < 100 && !dRsp_ready_pending;
|
||||
|
||||
|
||||
if (Verilated::gotFinish())
|
||||
|
|
@ -411,27 +394,27 @@ public:
|
|||
}
|
||||
|
||||
virtual void onReset(){
|
||||
top->iCmd_ready = 1;
|
||||
top->iRsp_ready = 1;
|
||||
top->iBus_cmd_ready = 1;
|
||||
top->iBus_rsp_ready = 1;
|
||||
}
|
||||
|
||||
virtual void preCycle(){
|
||||
if (top->iCmd_valid && top->iCmd_ready && !pending) {
|
||||
assertEq(top->iCmd_payload_pc & 3,0);
|
||||
if (top->iBus_cmd_valid && top->iBus_cmd_ready && !pending) {
|
||||
assertEq(top->iBus_cmd_payload_pc & 3,0);
|
||||
pending = true;
|
||||
ws->iBusAccess(top->iCmd_payload_pc,&inst_next,&error_next);
|
||||
ws->iBusAccess(top->iBus_cmd_payload_pc,&inst_next,&error_next);
|
||||
}
|
||||
}
|
||||
|
||||
virtual void postCycle(){
|
||||
top->iRsp_ready = !pending;
|
||||
if(pending && (!ws->iStall || VL_RANDOM_I(8) < 100)){
|
||||
top->iRsp_inst = inst_next;
|
||||
top->iBus_rsp_ready = !pending;
|
||||
if(pending && (!ws->iStall || VL_RANDOM_I(7) < 100)){
|
||||
top->iBus_rsp_inst = inst_next;
|
||||
pending = false;
|
||||
top->iRsp_ready = 1;
|
||||
top->iRsp_error = error_next;
|
||||
top->iBus_rsp_ready = 1;
|
||||
top->iBus_rsp_error = error_next;
|
||||
}
|
||||
if(ws->iStall) top->iCmd_ready = VL_RANDOM_I(8) < 100 && !pending;
|
||||
if(ws->iStall) top->iBus_cmd_ready = VL_RANDOM_I(7) < 100 && !pending;
|
||||
}
|
||||
};
|
||||
#endif
|
||||
|
|
@ -469,25 +452,72 @@ public:
|
|||
virtual void postCycle(){
|
||||
bool error;
|
||||
top->iBus_rsp_valid = 0;
|
||||
if(pendingCount != 0 && (!ws->iStall || VL_RANDOM_I(8) < 100)){
|
||||
if(pendingCount != 0 && (!ws->iStall || VL_RANDOM_I(7) < 100)){
|
||||
ws->iBusAccess(address,&top->iBus_rsp_payload_data,&error);
|
||||
top->iBus_rsp_payload_error = error;
|
||||
pendingCount--;
|
||||
address = (address & ~0x1F) + ((address + 4) & 0x1F);
|
||||
top->iBus_rsp_valid = 1;
|
||||
}
|
||||
if(ws->iStall) top->iBus_cmd_ready = VL_RANDOM_I(8) < 100 && pendingCount == 0;
|
||||
if(ws->iStall) top->iBus_cmd_ready = VL_RANDOM_I(7) < 100 && pendingCount == 0;
|
||||
}
|
||||
};
|
||||
#endif
|
||||
|
||||
void fillSimELements(Workspace *ws){
|
||||
#ifdef DBUS_SIMPLE
|
||||
class DBusSimple : public SimElement{
|
||||
public:
|
||||
uint32_t data_next = VL_RANDOM_I(32);
|
||||
bool error_next = false;
|
||||
bool pending = false;
|
||||
|
||||
Workspace *ws;
|
||||
VVexRiscv* top;
|
||||
DBusSimple(Workspace* ws){
|
||||
this->ws = ws;
|
||||
this->top = ws->top;
|
||||
}
|
||||
|
||||
virtual void onReset(){
|
||||
top->dBus_cmd_ready = 1;
|
||||
top->dBus_rsp_ready = 1;
|
||||
}
|
||||
|
||||
virtual void preCycle(){
|
||||
if (top->dBus_cmd_valid && top->dBus_cmd_ready && !pending) {
|
||||
pending = true;
|
||||
data_next = top->dBus_cmd_payload_data;
|
||||
ws->dBusAccess(top->dBus_cmd_payload_address,top->dBus_cmd_payload_wr,top->dBus_cmd_payload_size,&data_next,&error_next);
|
||||
}
|
||||
}
|
||||
|
||||
virtual void postCycle(){
|
||||
top->dBus_rsp_ready = 0;
|
||||
if(pending && (!ws->dStall || VL_RANDOM_I(7) < 100)){
|
||||
pending = false;
|
||||
top->dBus_rsp_ready = 1;
|
||||
top->dBus_rsp_data = data_next;
|
||||
top->dBus_rsp_error = error_next;
|
||||
} else{
|
||||
top->dBus_rsp_data = VL_RANDOM_I(32);
|
||||
}
|
||||
|
||||
if(ws->dStall) top->dBus_cmd_ready = VL_RANDOM_I(7) < 100 && !pending;
|
||||
}
|
||||
};
|
||||
#endif
|
||||
|
||||
|
||||
void Workspace::fillSimELements(){
|
||||
|
||||
#ifdef IBUS_SIMPLE
|
||||
ws->simElements.push_back(new IBusSimple(ws));
|
||||
simElements.push_back(new IBusSimple(this));
|
||||
#endif
|
||||
#ifdef IBUS_CACHED
|
||||
ws->simElements.push_back(new IBusCached(ws));
|
||||
simElements.push_back(new IBusCached(this));
|
||||
#endif
|
||||
#ifdef DBUS_SIMPLE
|
||||
simElements.push_back(new DBusSimple(this));
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
IBUS=IBUS_CACHED
|
||||
IBUS=IBUS_SIMPLE
|
||||
DBUS=DBUS_SIMPLE
|
||||
TRACE=no
|
||||
TRACE_START=0
|
||||
|
|
|
|||
Loading…
Reference in New Issue