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Merge remote-tracking branch 'origin/dBusCachedRelaxMmuTranslation'

This commit is contained in:
Dolu1990 2019-05-06 01:36:56 +02:00
parent 8f1b980337 91f6bf5139
commit 3094f8b349
2 changed files with 15 additions and 3 deletions
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6
src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
View File

@ -23,6 +23,7 @@ class DBusCachedPlugin(config : DataCacheConfig,
dBusCmdMasterPipe : Boolean = false,
dBusCmdSlavePipe : Boolean = false,
dBusRspSlavePipe : Boolean = false,
relaxedMemoryTranslationRegister : Boolean = false,
csrInfo : Boolean = false) extends Plugin[VexRiscv] with DBusAccessService {
import config._
@ -49,6 +50,7 @@ class DBusCachedPlugin(config : DataCacheConfig,
object MEMORY_LRSC extends Stageable(Bool)
object MEMORY_AMO extends Stageable(Bool)
object IS_DBUS_SHARING extends Stageable(Bool())
object MEMORY_VIRTUAL_ADDRESS extends Stageable(UInt(32 bits))
override def setup(pipeline: VexRiscv): Unit = {
import Riscv._
@ -212,6 +214,8 @@ class DBusCachedPlugin(config : DataCacheConfig,
when(cache.io.cpu.redo && arbitration.isValid && input(MEMORY_ENABLE)){
arbitration.haltItself := True
}
if(relaxedMemoryTranslationRegister) insert(MEMORY_VIRTUAL_ADDRESS) := cache.io.cpu.execute.address
}
memory plug new Area{
@ -219,7 +223,7 @@ class DBusCachedPlugin(config : DataCacheConfig,
cache.io.cpu.memory.isValid := arbitration.isValid && input(MEMORY_ENABLE)
cache.io.cpu.memory.isStuck := arbitration.isStuck
cache.io.cpu.memory.isRemoved := arbitration.removeIt
cache.io.cpu.memory.address := U(input(REGFILE_WRITE_DATA))
cache.io.cpu.memory.address := (if(relaxedMemoryTranslationRegister) input(MEMORY_VIRTUAL_ADDRESS) else U(input(REGFILE_WRITE_DATA)))
cache.io.cpu.memory.mmuBus <> mmuBus
cache.io.cpu.memory.mmuBus.rsp.isIoAccess setWhen(pipeline(DEBUG_BYPASS_CACHE) && !cache.io.cpu.memory.isWrite)

12
src/test/scala/vexriscv/TestIndividualFeatures.scala
View File

@ -396,11 +396,14 @@ class DBusDimension extends VexRiscvDimension("DBus") {
var wayCount = 0
val withLrSc = catchAll
val withAmo = catchAll && r.nextBoolean()
val dBusRspSlavePipe, relaxedMemoryTranslationRegister, earlyWaysHits = r.nextBoolean()
val dBusCmdMasterPipe, dBusCmdSlavePipe = false //As it create test bench issues
do{
cacheSize = 512 << r.nextInt(5)
wayCount = 1 << r.nextInt(3)
}while(cacheSize/wayCount < 512 || (catchAll && cacheSize/wayCount > 4096))
new VexRiscvPosition("Cached" + "S" + cacheSize + "W" + wayCount + "BPL" + bytePerLine) {
new VexRiscvPosition("Cached" + "S" + cacheSize + "W" + wayCount + "BPL" + bytePerLine + (if(dBusCmdMasterPipe) "Cmp " else "") + (if(dBusCmdSlavePipe) "Csp " else "") + (if(dBusRspSlavePipe) "Rsp " else "") + (if(relaxedMemoryTranslationRegister) "Rmtr " else "") + (if(earlyWaysHits) "Ewh " else "")) {
override def testParam = "DBUS=CACHED " + (if(withLrSc) "LRSC=yes " else "") + (if(withAmo) "AMO=yes " else "")
override def applyOn(config: VexRiscvConfig): Unit = {
@ -416,8 +419,13 @@ class DBusDimension extends VexRiscvDimension("DBus") {
catchIllegal = catchAll,
catchUnaligned = catchAll,
withLrSc = withLrSc,
withAmo = withAmo
withAmo = withAmo,
earlyWaysHits = earlyWaysHits
),
dBusCmdMasterPipe = dBusCmdMasterPipe,
dBusCmdSlavePipe = dBusCmdSlavePipe,
dBusRspSlavePipe = dBusRspSlavePipe,
relaxedMemoryTranslationRegister = relaxedMemoryTranslationRegister,
memoryTranslatorPortConfig = mmuConfig
)
}