readme ToC fix
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## Index
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- [Description](#description)
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- [Area / FMax](#area---fmax)
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- [Area usage and maximal frequency](#area-usage-and-maximal-frequency)
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- [Dependencies](#dependencies)
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- [CPU generation](#cpu-generation)
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- [Regression tests](#regression-tests)
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- [Interactive debug of the simulated CPU via GDB/OpenOCD in Verilator](#interactive-debug-of-the-simulated-cpu-via-gdb-openocd-in-verilator)
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- [Interactive debug of the simulated CPU via GDB and OpenOCD (Verilator sim)](#interactive-debug-of-the-simulated-cpu-via-gdb-and-openocd--verilator-sim-)
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- [Using eclipse to run the software and debug it](#using-eclipse-to-run-the-software-and-debug-it)
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- [Briey SoC](#briey-soc)
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- [Build the RISC-V GCC](#build-the-risc-v-gcc)
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@ -34,7 +34,7 @@ The hardware description of this CPU is done by using an very software oriented
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- There is an automatic a tool which allow plugins to insert data in the pipeline at a given stage, and allow other plugins to read it in another stages through automatic pipelining.
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- There is an service system which provide a very dynamic framework. As instance, a plugin could provide an exception service which could then be used by others plugins to emit exceptions from the pipeline.
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## Area / FMax
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## Area usage and maximal frequency
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The following number where obtains by synthesis the CPU as toplevel without any specific synthesis option to save area or to get better maximal frequency (neutral).
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The used CPU corresponding configuration can be find in src/scala/VexRiscv/demo.
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make clean run IBUS=IBUS_SIMPLE DBUS=DBUS_SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no
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```
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## Interactive debug of the simulated CPU via GDB/OpenOCD in Verilator
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## Interactive debug of the simulated CPU via GDB and OpenOCD (Verilator sim)
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It's as described to run tests, but you just have to add DEBUG_PLUGIN_EXTERNAL=yes in the make arguments.
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Work for the GenFull, but not for the GenSmallest as this configuration has no debug module.
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