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VexRiscv
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Merge remote-tracking branch 'origin/tigthlyCoupled' into dev

This commit is contained in:
Charles Papon 2019-10-03 12:33:27 +02:00
parent be18d8fa5a 5df56bea79
commit 319d162f67
2 changed files with 14 additions and 12 deletions
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18
src/main/scala/vexriscv/ip/InstructionCache.scala
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@ -22,7 +22,8 @@ case class InstructionCacheConfig( cacheSize : Int,
asyncTagMemory : Boolean, asyncTagMemory : Boolean,
twoCycleCache : Boolean = true, twoCycleCache : Boolean = true,
twoCycleRam : Boolean = false, twoCycleRam : Boolean = false,
preResetFlush : Boolean = false){ preResetFlush : Boolean = false,
bypassGen : Boolean = false ){
assert(!(twoCycleRam && !twoCycleCache)) assert(!(twoCycleRam && !twoCycleCache))
@ -108,8 +109,8 @@ case class InstructionCacheCpuFetch(p : InstructionCacheConfig) extends Bundle w
val isRemoved = Bool() val isRemoved = Bool()
val pc = UInt(p.addressWidth bits) val pc = UInt(p.addressWidth bits)
val data = Bits(p.cpuDataWidth bits) val data = Bits(p.cpuDataWidth bits)
val dataBypassValid = Bool() val dataBypassValid = p.bypassGen generate Bool()
val dataBypass = Bits(p.cpuDataWidth bits) val dataBypass = p.bypassGen generate Bits(p.cpuDataWidth bits)
val mmuBus = MemoryTranslatorBus() val mmuBus = MemoryTranslatorBus()
val physicalAddress = UInt(p.addressWidth bits) val physicalAddress = UInt(p.addressWidth bits)
val cacheMiss, error, mmuRefilling, mmuException, isUser = ifGen(!p.twoCycleCache)(Bool) val cacheMiss, error, mmuRefilling, mmuException, isUser = ifGen(!p.twoCycleCache)(Bool)
@ -415,15 +416,16 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
val id = OHToUInt(hits) val id = OHToUInt(hits)
val error = read.waysValues.map(_.tag.error).read(id) val error = read.waysValues.map(_.tag.error).read(id)
val data = read.waysValues.map(_.data).read(id) val data = read.waysValues.map(_.data).read(id)
val word = data.subdivideIn(cpuDataWidth bits).read(io.cpu.fetch.pc(memWordToCpuWordRange)) val word = if(cpuDataWidth == memDataWidth) CombInit(data) else data.subdivideIn(cpuDataWidth bits).read(io.cpu.fetch.pc(memWordToCpuWordRange))
io.cpu.fetch.data := (io.cpu.fetch.dataBypassValid ? io.cpu.fetch.dataBypass | word) io.cpu.fetch.data := (if(p.bypassGen) (io.cpu.fetch.dataBypassValid ? io.cpu.fetch.dataBypass | word) else word)
if(twoCycleCache){ if(twoCycleCache){
io.cpu.decode.data := RegNextWhen(io.cpu.fetch.data,!io.cpu.decode.isStuck) io.cpu.decode.data := RegNextWhen(io.cpu.fetch.data,!io.cpu.decode.isStuck)
} }
} }
if(twoCycleRam && wayCount == 1){ if(twoCycleRam && wayCount == 1){
io.cpu.fetch.data := (io.cpu.fetch.dataBypassValid ? io.cpu.fetch.dataBypass | read.waysValues.head.data.subdivideIn(cpuDataWidth bits).read(io.cpu.fetch.pc(memWordToCpuWordRange))) val cacheData = if(cpuDataWidth == memDataWidth) CombInit(read.waysValues.head.data) else read.waysValues.head.data.subdivideIn(cpuDataWidth bits).read(io.cpu.fetch.pc(memWordToCpuWordRange))
io.cpu.fetch.data := (if(p.bypassGen) (io.cpu.fetch.dataBypassValid ? io.cpu.fetch.dataBypass | cacheData) else cacheData)
} }
io.cpu.fetch.mmuBus.cmd.isValid := io.cpu.fetch.isValid io.cpu.fetch.mmuBus.cmd.isValid := io.cpu.fetch.isValid
@ -458,8 +460,8 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
val id = OHToUInt(hits) val id = OHToUInt(hits)
val error = tags(id).error val error = tags(id).error
val data = fetchStage.read.waysValues.map(way => stage(way.data)).read(id) val data = fetchStage.read.waysValues.map(way => stage(way.data)).read(id)
val word = data.subdivideIn(cpuDataWidth bits).read(io.cpu.decode.pc(memWordToCpuWordRange)) val word = if(cpuDataWidth == memDataWidth) data else data.subdivideIn(cpuDataWidth bits).read(io.cpu.decode.pc(memWordToCpuWordRange))
when(stage(io.cpu.fetch.dataBypassValid)){ if(p.bypassGen) when(stage(io.cpu.fetch.dataBypassValid)){
word := stage(io.cpu.fetch.dataBypass) word := stage(io.cpu.fetch.dataBypass)
} }
io.cpu.decode.data := word io.cpu.decode.data := word

8
src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala
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@ -61,7 +61,7 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
var redoBranch : Flow[UInt] = null var redoBranch : Flow[UInt] = null
var decodeExceptionPort : Flow[ExceptionCause] = null var decodeExceptionPort : Flow[ExceptionCause] = null
val tightlyCoupledPorts = ArrayBuffer[TightlyCoupledPort]() val tightlyCoupledPorts = ArrayBuffer[TightlyCoupledPort]()
def tightlyGen = tightlyCoupledPorts.nonEmpty
def newTightlyCoupledPort(p : TightlyCoupledPortParameter) = { def newTightlyCoupledPort(p : TightlyCoupledPortParameter) = {
val port = TightlyCoupledPort(p, null) val port = TightlyCoupledPort(p, null)
@ -125,7 +125,7 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
import pipeline.config._ import pipeline.config._
pipeline plug new FetchArea(pipeline) { pipeline plug new FetchArea(pipeline) {
val cache = new InstructionCache(IBusCachedPlugin.this.config) val cache = new InstructionCache(IBusCachedPlugin.this.config.copy(bypassGen = tightlyGen))
iBus = master(new InstructionCacheMemBus(IBusCachedPlugin.this.config)).setName("iBus") iBus = master(new InstructionCacheMemBus(IBusCachedPlugin.this.config)).setName("iBus")
iBus <> cache.io.mem iBus <> cache.io.mem
iBus.cmd.address.allowOverride := cache.io.mem.cmd.address iBus.cmd.address.allowOverride := cache.io.mem.cmd.address
@ -165,8 +165,8 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
val tightlyCoupledHits = RegNextWhen(s0.tightlyCoupledHits, stages(1).input.ready) val tightlyCoupledHits = RegNextWhen(s0.tightlyCoupledHits, stages(1).input.ready)
val tightlyCoupledHit = RegNextWhen(s0.tightlyCoupledHit, stages(1).input.ready) val tightlyCoupledHit = RegNextWhen(s0.tightlyCoupledHit, stages(1).input.ready)
cache.io.cpu.fetch.dataBypassValid := tightlyCoupledHit if(tightlyGen) cache.io.cpu.fetch.dataBypassValid := tightlyCoupledHit
cache.io.cpu.fetch.dataBypass := (if(tightlyCoupledPorts.isEmpty) B(0) else MuxOH(tightlyCoupledHits, tightlyCoupledPorts.map(e => CombInit(e.bus.data)))) if(tightlyGen) cache.io.cpu.fetch.dataBypass := MuxOH(tightlyCoupledHits, tightlyCoupledPorts.map(e => CombInit(e.bus.data)))
//Connect fetch cache side //Connect fetch cache side
cache.io.cpu.fetch.isValid := stages(1).input.valid && !tightlyCoupledHit cache.io.cpu.fetch.isValid := stages(1).input.valid && !tightlyCoupledHit