Got VexRiscvSmpLitexCluster refractoring to work
This commit is contained in:
Dolu1990
parent
0da94ac66f
commit
32539dfe6d
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@ -0,0 +1,156 @@
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package vexriscv
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import spinal.core._
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import spinal.lib.bus.bmb.{Bmb, BmbAccessCapabilities, BmbAccessParameter, BmbImplicitDebugDecoder, BmbParameter, BmbSmpInterconnectGenerator}
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import spinal.lib.bus.misc.AddressMapping
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import spinal.lib.com.jtag.{Jtag, JtagTapInstructionCtrl}
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import spinal.lib.generator._
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import spinal.lib.slave
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import vexriscv.plugin._
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object VexRiscvBmbGenerator{
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val DEBUG_NONE = 0
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val DEBUG_JTAG = 1
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val DEBUG_JTAG_CTRL = 2
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val DEBUG_BUS = 3
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val DEBUG_BMB = 4
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}
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case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbSmpInterconnectGenerator = null) extends Generator {
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import VexRiscvBmbGenerator._
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val config = Handle[VexRiscvConfig]
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val withDebug = Handle[Int]
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val debugClockDomain = Handle[ClockDomain]
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val debugReset = Handle[Bool]
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val debugAskReset = Handle[() => Unit]
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val hardwareBreakpointCount = Handle(0)
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val iBus, dBus = product[Bmb]
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val externalInterrupt = product[Bool]
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val externalSupervisorInterrupt = product[Bool]
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val timerInterrupt = product[Bool]
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val softwareInterrupt = product[Bool]
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def setTimerInterrupt(that: Handle[Bool]) = Dependable(that, timerInterrupt){timerInterrupt := that}
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def setSoftwareInterrupt(that: Handle[Bool]) = Dependable(that, softwareInterrupt){softwareInterrupt := that}
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def disableDebug() = {
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withDebug.load(DEBUG_NONE)
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}
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def enableJtag(debugCd : ClockDomainResetGenerator, resetCd : ClockDomainResetGenerator) : Unit = debugCd{
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this.debugClockDomain.merge(debugCd.outputClockDomain)
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val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH)
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debugAskReset.load(null)
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withDebug.load(DEBUG_JTAG)
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}
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def enableJtagInstructionCtrl(debugCd : ClockDomainResetGenerator, resetCd : ClockDomainResetGenerator) : Unit = debugCd{
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this.debugClockDomain.merge(debugCd.outputClockDomain)
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val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH)
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debugAskReset.load(null)
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withDebug.load(DEBUG_JTAG_CTRL)
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dependencies += jtagClockDomain
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}
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def enableDebugBus(debugCd : ClockDomainResetGenerator, resetCd : ClockDomainResetGenerator) : Unit = debugCd{
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this.debugClockDomain.merge(debugCd.outputClockDomain)
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val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH)
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debugAskReset.load(null)
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withDebug.load(DEBUG_BUS)
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}
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val debugBmbAccessSource = Handle[BmbAccessCapabilities]
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val debugBmbAccessRequirements = Handle[BmbAccessParameter]
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def enableDebugBmb(debugCd : ClockDomainResetGenerator, resetCd : ClockDomainResetGenerator, mapping : AddressMapping)(implicit debugMaster : BmbImplicitDebugDecoder = null) : Unit = debugCd{
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this.debugClockDomain.merge(debugCd.outputClockDomain)
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val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH)
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debugAskReset.load(null)
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withDebug.load(DEBUG_BMB)
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val slaveModel = interconnectSmp.addSlave(
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accessSource = debugBmbAccessSource,
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accessCapabilities = debugBmbAccessSource.derivate(DebugExtensionBus.getBmbAccessParameter(_)),
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accessRequirements = debugBmbAccessRequirements,
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bus = debugBmb,
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mapping = mapping
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)
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slaveModel.onClockDomain(debugCd.outputClockDomain)
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debugBmb.derivatedFrom(debugBmbAccessRequirements)(Bmb(_))
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if(debugMaster != null) interconnectSmp.addConnection(debugMaster.bus, debugBmb)
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dependencies += debugBmb
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}
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dependencies ++= List(config)
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dependencies += Dependable(withDebug) {
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if (withDebug.get != DEBUG_NONE) {
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dependencies ++= List(debugClockDomain, debugAskReset)
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}
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}
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val jtag = add task (withDebug.get == DEBUG_JTAG generate slave(Jtag()))
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val jtagInstructionCtrl = withDebug.produce(withDebug.get == DEBUG_JTAG_CTRL generate JtagTapInstructionCtrl())
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val debugBus = withDebug.produce(withDebug.get == DEBUG_BUS generate DebugExtensionBus())
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val debugBmb = Handle[Bmb]
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val jtagClockDomain = Handle[ClockDomain]
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val logic = add task new Area {
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withDebug.get != DEBUG_NONE generate new Area {
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config.add(new DebugPlugin(debugClockDomain, hardwareBreakpointCount))
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}
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val cpu = new VexRiscv(config)
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for (plugin <- cpu.plugins) plugin match {
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case plugin: IBusSimplePlugin => iBus.load(plugin.iBus.toBmb())
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case plugin: DBusSimplePlugin => dBus.load(plugin.dBus.toBmb())
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case plugin: IBusCachedPlugin => iBus.load(plugin.iBus.toBmb())
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case plugin: DBusCachedPlugin => dBus.load(plugin.dBus.toBmb())
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case plugin: CsrPlugin => {
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externalInterrupt load plugin.externalInterrupt
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timerInterrupt load plugin.timerInterrupt
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softwareInterrupt load plugin.softwareInterrupt
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if (plugin.config.supervisorGen) externalSupervisorInterrupt load plugin.externalInterruptS
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}
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case plugin: DebugPlugin => plugin.debugClockDomain {
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if(debugAskReset.get != null) when(RegNext(plugin.io.resetOut)) {
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debugAskReset.get()
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} else {
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debugReset.load(RegNext(plugin.io.resetOut))
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}
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withDebug.get match {
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case DEBUG_JTAG => jtag <> plugin.io.bus.fromJtag()
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case DEBUG_JTAG_CTRL => jtagInstructionCtrl <> plugin.io.bus.fromJtagInstructionCtrl(jtagClockDomain)
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case DEBUG_BUS => debugBus <> plugin.io.bus
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case DEBUG_BMB => debugBmb >> plugin.io.bus.fromBmb()
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}
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}
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case _ =>
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}
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}
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val parameterGenerator = new Generator {
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val iBusParameter, dBusParameter = product[BmbParameter]
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dependencies += config
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add task {
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for (plugin <- config.plugins) plugin match {
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case plugin: IBusSimplePlugin => iBusParameter.load(IBusSimpleBus.getBmbParameter())
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case plugin: DBusSimplePlugin => dBusParameter.load(DBusSimpleBus.getBmbParameter())
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case plugin: IBusCachedPlugin => iBusParameter.load(plugin.config.getBmbParameter())
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case plugin: DBusCachedPlugin => dBusParameter.load(plugin.config.getBmbParameter())
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case _ =>
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}
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}
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}
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if(interconnectSmp != null){
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interconnectSmp.addMaster(accessRequirements = parameterGenerator.iBusParameter.derivate(_.access), bus = iBus)
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interconnectSmp.addMaster(accessRequirements = parameterGenerator.dBusParameter.derivate(_.access), bus = dBus)
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}
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}
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@ -9,6 +9,7 @@ import spinal.lib._
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import spinal.lib.bus.bmb.sim.{BmbMemoryMultiPort, BmbMemoryTester}
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import spinal.lib.bus.misc.{AddressMapping, DefaultMapping, SizeMapping}
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import spinal.lib.eda.bench.Bench
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import spinal.lib.generator.{Generator, Handle}
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import spinal.lib.misc.Clint
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import spinal.lib.sim.{SimData, SparseMemory, StreamDriver, StreamMonitor, StreamReadyRandomizer}
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import vexriscv.{VexRiscv, VexRiscvConfig}
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@ -244,4 +245,44 @@ object BmbToLiteDramTester extends App{
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val tester = new BmbMemoryTester(dut.io.input, dut.clockDomain, rspCounterTarget = 3000)
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dut.io.output.simSlave(tester.memory.memory, dut.clockDomain)
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}
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}
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}
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case class BmbToLiteDramGenerator(mapping : AddressMapping)(implicit interconnect : BmbSmpInterconnectGenerator) extends Generator{
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val liteDramParameter = createDependency[LiteDramNativeParameter]
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val bmb = produce(logic.io.input)
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val dram = produceIo(logic.io.output)
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val accessSource = Handle[BmbAccessCapabilities]
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val accessRequirements = createDependency[BmbAccessParameter]
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interconnect.addSlave(
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accessSource = accessSource,
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accessCapabilities = accessSource,
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accessRequirements = accessRequirements,
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bus = bmb,
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mapping = mapping
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)
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val logic = add task BmbToLiteDram(
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bmbParameter = accessRequirements.toBmbParameter(),
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liteDramParameter = liteDramParameter,
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wdataFifoSize = 32,
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rdataFifoSize = 32
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)
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}
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case class BmbToWishboneGenerator(mapping : AddressMapping)(implicit interconnect : BmbSmpInterconnectGenerator) extends Generator{
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val bmb = produce(logic.io.input)
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val wishbone = produce(logic.io.output)
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val accessSource = Handle[BmbAccessCapabilities]
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val accessRequirements = createDependency[BmbAccessParameter]
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interconnect.addSlave(
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accessSource = accessSource,
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accessCapabilities = accessSource,
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accessRequirements = accessRequirements,
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bus = bmb,
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mapping = mapping
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)
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val logic = add task BmbToWishbone(
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p = accessRequirements.toBmbParameter()
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)
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}
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@ -5,21 +5,110 @@ import spinal.core._
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import spinal.core.sim.{onSimEnd, simSuccess}
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import spinal.lib._
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import spinal.lib.bus.bmb.sim.BmbMemoryAgent
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import spinal.lib.bus.bmb.{Bmb, BmbArbiter, BmbDecoder, BmbExclusiveMonitor, BmbInvalidateMonitor, BmbParameter}
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import spinal.lib.bus.misc.SizeMapping
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import spinal.lib.com.jtag.{Jtag, JtagTapInstructionCtrl}
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import spinal.lib.bus.bmb._
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import spinal.lib.bus.misc.{DefaultMapping, SizeMapping}
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import spinal.lib.bus.wishbone.{Wishbone, WishboneConfig, WishboneToBmb, WishboneToBmbGenerator}
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import spinal.lib.com.jtag.{Jtag, JtagInstructionDebuggerGenerator, JtagTapInstructionCtrl}
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import spinal.lib.com.jtag.sim.JtagTcp
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import spinal.lib.com.jtag.xilinx.Bscane2BmbMasterGenerator
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import spinal.lib.generator.Handle
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import spinal.lib.misc.plic.PlicMapping
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import spinal.lib.system.debugger.SystemDebuggerConfig
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import vexriscv.ip.{DataCacheAck, DataCacheConfig, DataCacheMemBus, InstructionCache, InstructionCacheConfig}
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import vexriscv.plugin.{BranchPlugin, CsrAccess, CsrPlugin, CsrPluginConfig, DBusCachedPlugin, DBusSimplePlugin, DYNAMIC_TARGET, DebugPlugin, DecoderSimplePlugin, FullBarrelShifterPlugin, HazardSimplePlugin, IBusCachedPlugin, IBusSimplePlugin, IntAluPlugin, MmuPlugin, MmuPortConfig, MulDivIterativePlugin, MulPlugin, RegFilePlugin, STATIC, SrcPlugin, YamlPlugin}
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import vexriscv.{Riscv, VexRiscv, VexRiscvConfig, plugin}
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import vexriscv.{Riscv, VexRiscv, VexRiscvBmbGenerator, VexRiscvConfig, plugin}
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import scala.collection.mutable
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import scala.collection.mutable.ArrayBuffer
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import spinal.lib.generator._
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case class VexRiscvSmpClusterParameter( cpuConfigs : Seq[VexRiscvConfig])
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class VexRiscvSmpClusterBase(p : VexRiscvSmpClusterParameter) extends Generator{
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val cpuCount = p.cpuConfigs.size
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val debugCd = ClockDomainResetGenerator()
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debugCd.holdDuration.load(4095)
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debugCd.makeExternal()
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val systemCd = ClockDomainResetGenerator()
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systemCd.holdDuration.load(63)
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systemCd.setInput(debugCd)
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this.onClockDomain(systemCd.outputClockDomain)
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implicit val interconnect = BmbSmpInterconnectGenerator()
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val debugBridge = JtagInstructionDebuggerGenerator() onClockDomain(debugCd.outputClockDomain)
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debugBridge.jtagClockDomain.load(ClockDomain.external("jtag", withReset = false))
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val debugPort = debugBridge.produceIo(debugBridge.logic.jtagBridge.io.ctrl)
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val exclusiveMonitor = BmbExclusiveMonitorGenerator()
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val invalidationMonitor = BmbInvalidateMonitorGenerator()
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interconnect.addConnection(exclusiveMonitor.output, invalidationMonitor.input)
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interconnect.masters(invalidationMonitor.output).withOutOfOrderDecoder()
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val cores = for(cpuId <- 0 until cpuCount) yield new Area{
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val cpu = VexRiscvBmbGenerator()
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cpu.config.load(p.cpuConfigs(cpuId))
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interconnect.addConnection(
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cpu.dBus -> List(exclusiveMonitor.input)
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)
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cpu.enableDebugBmb(
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debugCd = debugCd,
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resetCd = systemCd,
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mapping = SizeMapping(cpuId*0x1000, 0x1000)
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)
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interconnect.addConnection(debugBridge.bmb, cpu.debugBmb)
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}
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}
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class VexRiscvSmpClusterWithPeripherals(p : VexRiscvSmpClusterParameter) extends VexRiscvSmpClusterBase(p) {
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val peripheralBridge = BmbToWishboneGenerator(DefaultMapping)
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val peripheral = peripheralBridge.produceIo(peripheralBridge.logic.io.output)
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interconnect.slaves(peripheralBridge.bmb).forceAccessSourceDataWidth(32)
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val plic = BmbPlicGenerator(0)
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plic.priorityWidth.load(2)
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plic.mapping.load(PlicMapping.sifive)
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val plicWishboneBridge = WishboneToBmbGenerator()
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val plicWishbone = plicWishboneBridge.produceIo(plicWishboneBridge.logic.io.input)
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plicWishboneBridge.config.load(WishboneConfig(20, 32))
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interconnect.addConnection(plicWishboneBridge.bmb, plic.bus)
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val clint = BmbClintGenerator(0)
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val clintWishboneBridge = WishboneToBmbGenerator()
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val clintWishbone = clintWishboneBridge.produceIo(clintWishboneBridge.logic.io.input)
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clintWishboneBridge.config.load(WishboneConfig(14, 32))
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interconnect.addConnection(clintWishboneBridge.bmb, clint.bus)
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val interrupts = add task (in Bits(32 bits))
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for(i <- 1 to 31) yield plic.addInterrupt(interrupts.derivate(_.apply(i)), i)
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for ((core, cpuId) <- cores.zipWithIndex) {
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core.cpu.setTimerInterrupt(clint.timerInterrupt(cpuId))
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core.cpu.setSoftwareInterrupt(clint.softwareInterrupt(cpuId))
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plic.priorityWidth.load(2)
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plic.mapping.load(PlicMapping.sifive)
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plic.addTarget(core.cpu.externalInterrupt)
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plic.addTarget(core.cpu.externalSupervisorInterrupt)
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List(clint.logic, core.cpu.logic).produce {
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for (plugin <- core.cpu.config.plugins) plugin match {
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case plugin: CsrPlugin if plugin.utime != null => plugin.utime := clint.logic.io.time
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case _ =>
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}
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}
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}
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clint.cpuCount.load(cpuCount)
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}
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//
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//case class VexRiscvSmpClusterParameter( cpuConfigs : Seq[VexRiscvConfig])
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//
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//case class VexRiscvSmpCluster(p : VexRiscvSmpClusterParameter,
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// debugClockDomain : ClockDomain) extends Component{
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// val dBusParameter = p.cpuConfigs.head.plugins.find(_.isInstanceOf[DBusCachedPlugin]).get.asInstanceOf[DBusCachedPlugin].config.getBmbParameter()
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@ -1,305 +1,150 @@
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//package vexriscv.demo.smp
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//
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//import spinal.core._
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//import spinal.lib.bus.bmb._
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//import spinal.lib.bus.wishbone.{Wishbone, WishboneConfig, WishboneSlaveFactory}
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//import spinal.lib.com.jtag.{Jtag, JtagTapInstructionCtrl}
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//import spinal.lib._
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//import spinal.lib.bus.bmb.sim.{BmbMemoryMultiPort, BmbMemoryTester}
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//import spinal.lib.bus.misc.{AddressMapping, DefaultMapping, SizeMapping}
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//import spinal.lib.eda.bench.Bench
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//import spinal.lib.misc.Clint
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//import spinal.lib.misc.plic.{PlicGatewayActiveHigh, PlicMapper, PlicMapping, PlicTarget}
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//import spinal.lib.sim.{SimData, SparseMemory, StreamDriver, StreamMonitor, StreamReadyRandomizer}
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//import spinal.lib.system.debugger.{JtagBridgeNoTap, SystemDebugger, SystemDebuggerConfig}
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//import vexriscv.demo.smp.VexRiscvLitexSmpClusterOpenSbi.{cpuCount, parameter}
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//import vexriscv.demo.smp.VexRiscvSmpClusterGen.vexRiscvConfig
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//import vexriscv.{VexRiscv, VexRiscvConfig}
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//import vexriscv.plugin.{CsrPlugin, DBusCachedPlugin, DebugPlugin, IBusCachedPlugin}
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//
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//import scala.collection.mutable
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//import scala.util.Random
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//
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//
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//case class VexRiscvLitexSmpClusterParameter( cluster : VexRiscvSmpClusterParameter,
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// liteDram : LiteDramNativeParameter,
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// liteDramMapping : AddressMapping)
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//
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package vexriscv.demo.smp
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import spinal.core._
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import spinal.lib.bus.bmb._
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import spinal.lib.bus.misc.{AddressMapping, DefaultMapping, SizeMapping}
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import spinal.lib.sim.SparseMemory
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import vexriscv.demo.smp.VexRiscvSmpClusterGen.vexRiscvConfig
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case class VexRiscvLitexSmpClusterParameter( cluster : VexRiscvSmpClusterParameter,
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liteDram : LiteDramNativeParameter,
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liteDramMapping : AddressMapping)
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class VexRiscvLitexSmpCluster(p : VexRiscvLitexSmpClusterParameter) extends VexRiscvSmpClusterWithPeripherals(p.cluster) {
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val iArbiter = BmbSmpBridgeGenerator()
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val iBridge = BmbToLiteDramGenerator(p.liteDramMapping)
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val dBridge = BmbToLiteDramGenerator(p.liteDramMapping)
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for(core <- cores) interconnect.addConnection(core.cpu.iBus -> List(iArbiter.bmb))
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interconnect.addConnection(
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iArbiter.bmb -> List(iBridge.bmb, peripheralBridge.bmb),
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invalidationMonitor.output -> List(dBridge.bmb, peripheralBridge.bmb)
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)
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interconnect.masters(invalidationMonitor.output).withOutOfOrderDecoder()
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dBridge.liteDramParameter.load(p.liteDram)
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iBridge.liteDramParameter.load(p.liteDram)
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// Interconnect pipelining (FMax)
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for(core <- cores) {
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interconnect.setPipelining(core.cpu.dBus)(cmdValid = true, cmdReady = true, rspValid = true)
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interconnect.setPipelining(core.cpu.iBus)(cmdHalfRate = true, rspValid = true)
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interconnect.setPipelining(iArbiter.bmb)(cmdHalfRate = true, rspValid = true)
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}
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interconnect.setPipelining(invalidationMonitor.output)(cmdValid = true, cmdReady = true, rspValid = true)
|
||||
interconnect.setPipelining(peripheralBridge.bmb)(cmdHalfRate = true, rspValid = true)
|
||||
}
|
||||
|
||||
|
||||
object VexRiscvLitexSmpClusterGen extends App {
|
||||
for(cpuCount <- List(1,2,4,8)) {
|
||||
def parameter = VexRiscvLitexSmpClusterParameter(
|
||||
cluster = VexRiscvSmpClusterParameter(
|
||||
cpuConfigs = List.tabulate(cpuCount) { hartId =>
|
||||
vexRiscvConfig(
|
||||
hartId = hartId,
|
||||
ioRange = address => address.msb,
|
||||
resetVector = 0
|
||||
)
|
||||
}
|
||||
),
|
||||
liteDram = LiteDramNativeParameter(addressWidth = 32, dataWidth = 128),
|
||||
liteDramMapping = SizeMapping(0x40000000l, 0x40000000l)
|
||||
)
|
||||
|
||||
def dutGen = {
|
||||
val toplevel = new VexRiscvLitexSmpCluster(
|
||||
p = parameter
|
||||
).toComponent()
|
||||
toplevel
|
||||
}
|
||||
|
||||
val genConfig = SpinalConfig().addStandardMemBlackboxing(blackboxByteEnables)
|
||||
// genConfig.generateVerilog(Bench.compressIo(dutGen))
|
||||
genConfig.generateVerilog(dutGen.setDefinitionName(s"VexRiscvLitexSmpCluster_${cpuCount}c"))
|
||||
}
|
||||
}
|
||||
|
||||
////addAttribute("""mark_debug = "true"""")
|
||||
//case class VexRiscvLitexSmpCluster(p : VexRiscvLitexSmpClusterParameter,
|
||||
// debugClockDomain : ClockDomain,
|
||||
// jtagClockDomain : ClockDomain) extends Component{
|
||||
//
|
||||
// val peripheralWishboneConfig = WishboneConfig(
|
||||
// addressWidth = 30,
|
||||
// dataWidth = 32,
|
||||
// selWidth = 4,
|
||||
// useERR = true,
|
||||
// useBTE = true,
|
||||
// useCTI = true
|
||||
// )
|
||||
//
|
||||
// val io = new Bundle {
|
||||
// val dMem = master(LiteDramNative(p.liteDram))
|
||||
// val iMem = master(LiteDramNative(p.liteDram))
|
||||
// val peripheral = master(Wishbone(peripheralWishboneConfig))
|
||||
// val clint = slave(Wishbone(Clint.getWisboneConfig()))
|
||||
// val plic = slave(Wishbone(WishboneConfig(addressWidth = 20, dataWidth = 32)))
|
||||
// val interrupts = in Bits(32 bits)
|
||||
// val jtagInstruction = slave(JtagTapInstructionCtrl())
|
||||
// val debugReset = out Bool()
|
||||
// }
|
||||
// val cpuCount = p.cluster.cpuConfigs.size
|
||||
// val clint = Clint(cpuCount)
|
||||
// clint.driveFrom(WishboneSlaveFactory(io.clint))
|
||||
//
|
||||
// val cluster = VexRiscvSmpCluster(p.cluster, debugClockDomain)
|
||||
// cluster.io.debugReset <> io.debugReset
|
||||
// cluster.io.timerInterrupts <> B(clint.harts.map(_.timerInterrupt))
|
||||
// cluster.io.softwareInterrupts <> B(clint.harts.map(_.softwareInterrupt))
|
||||
// cluster.io.time := clint.time
|
||||
//
|
||||
// val debug = debugClockDomain on new Area{
|
||||
// val jtagConfig = SystemDebuggerConfig()
|
||||
// val jtagBridge = new JtagBridgeNoTap(
|
||||
// c = jtagConfig,
|
||||
// jtagClockDomain = jtagClockDomain
|
||||
// )
|
||||
// jtagBridge.io.ctrl << io.jtagInstruction
|
||||
//
|
||||
// val debugger = new SystemDebugger(jtagConfig)
|
||||
// debugger.io.remote <> jtagBridge.io.remote
|
||||
//
|
||||
// cluster.io.debugBus << debugger.io.mem.toBmb()
|
||||
// }
|
||||
//
|
||||
// val dBusDecoder = BmbDecoderOutOfOrder(
|
||||
// p = cluster.io.dMem.p,
|
||||
// mappings = Seq(DefaultMapping, p.liteDramMapping),
|
||||
// capabilities = Seq(cluster.io.dMem.p, cluster.io.dMem.p),
|
||||
// pendingRspTransactionMax = 32
|
||||
// )
|
||||
//// val dBusDecoder = BmbDecoderOut(
|
||||
//// p = cluster.io.dMem.p,
|
||||
//// mappings = Seq(DefaultMapping, p.liteDramMapping),
|
||||
//// capabilities = Seq(cluster.io.dMem.p, cluster.io.dMem.p),
|
||||
//// pendingMax = 31
|
||||
//// )
|
||||
// dBusDecoder.io.input << cluster.io.dMem.pipelined(cmdValid = true, cmdReady = true, rspValid = true)
|
||||
// val dMemBridge = io.dMem.fromBmb(dBusDecoder.io.outputs(1), wdataFifoSize = 32, rdataFifoSize = 32)
|
||||
//
|
||||
// val iBusArbiterParameter = cluster.iBusParameter.copy(sourceWidth = log2Up(cpuCount))
|
||||
// val iBusArbiter = BmbArbiter(
|
||||
// p = iBusArbiterParameter,
|
||||
// portCount = cpuCount,
|
||||
// lowerFirstPriority = false
|
||||
// )
|
||||
//
|
||||
// (iBusArbiter.io.inputs, cluster.io.iMems).zipped.foreach(_ << _.pipelined(cmdHalfRate = true, rspValid = true))
|
||||
//
|
||||
// val iBusDecoder = BmbDecoder(
|
||||
// p = iBusArbiter.io.output.p,
|
||||
// mappings = Seq(DefaultMapping, p.liteDramMapping),
|
||||
// capabilities = Seq(iBusArbiterParameter, iBusArbiterParameter),
|
||||
// pendingMax = 15
|
||||
// )
|
||||
// iBusDecoder.io.input << iBusArbiter.io.output.pipelined(cmdValid = true)
|
||||
//
|
||||
// val iMem = LiteDramNative(p.liteDram)
|
||||
// io.iMem.fromBmb(iBusDecoder.io.outputs(1), wdataFifoSize = 0, rdataFifoSize = 32)
|
||||
//
|
||||
//
|
||||
// val iBusDecoderToPeripheral = iBusDecoder.io.outputs(0).resize(dataWidth = 32).pipelined(cmdHalfRate = true, rspValid = true)
|
||||
// val dBusDecoderToPeripheral = dBusDecoder.io.outputs(0).resize(dataWidth = 32).pipelined(cmdHalfRate = true, rspValid = true)
|
||||
//
|
||||
// val peripheralAccessLength = Math.max(iBusDecoder.io.outputs(0).p.lengthWidth, dBusDecoder.io.outputs(0).p.lengthWidth)
|
||||
// val peripheralArbiter = BmbArbiter(
|
||||
// p = dBusDecoder.io.outputs(0).p.copy(
|
||||
// sourceWidth = List(iBusDecoderToPeripheral, dBusDecoderToPeripheral).map(_.p.sourceWidth).max + 1,
|
||||
// contextWidth = List(iBusDecoderToPeripheral, dBusDecoderToPeripheral).map(_.p.contextWidth).max,
|
||||
// lengthWidth = peripheralAccessLength,
|
||||
// dataWidth = 32
|
||||
// ),
|
||||
// portCount = 2,
|
||||
// lowerFirstPriority = true
|
||||
// )
|
||||
// peripheralArbiter.io.inputs(0) << iBusDecoderToPeripheral
|
||||
// peripheralArbiter.io.inputs(1) << dBusDecoderToPeripheral
|
||||
//
|
||||
// val peripheralWishbone = peripheralArbiter.io.output.pipelined(cmdValid = true).toWishbone()
|
||||
// io.peripheral << peripheralWishbone
|
||||
//
|
||||
// val plic = new Area{
|
||||
// val priorityWidth = 2
|
||||
//
|
||||
// val gateways = for(i <- 1 until 32) yield PlicGatewayActiveHigh(
|
||||
// source = io.interrupts(i),
|
||||
// id = i,
|
||||
// priorityWidth = priorityWidth
|
||||
// )
|
||||
//
|
||||
// val bus = WishboneSlaveFactory(io.plic)
|
||||
//
|
||||
// val targets = for(i <- 0 until cpuCount) yield new Area{
|
||||
// val machine = PlicTarget(
|
||||
// gateways = gateways,
|
||||
// priorityWidth = priorityWidth
|
||||
// )
|
||||
// val supervisor = PlicTarget(
|
||||
// gateways = gateways,
|
||||
// priorityWidth = priorityWidth
|
||||
// )
|
||||
//
|
||||
// cluster.io.externalInterrupts(i) := machine.iep
|
||||
// cluster.io.externalSupervisorInterrupts(i) := supervisor.iep
|
||||
// }
|
||||
//
|
||||
// val bridge = PlicMapper(bus, PlicMapping.sifive)(
|
||||
// gateways = gateways,
|
||||
// targets = targets.flatMap(t => List(t.machine, t.supervisor))
|
||||
// )
|
||||
// }
|
||||
//}
|
||||
//
|
||||
//object VexRiscvLitexSmpClusterGen extends App {
|
||||
// for(cpuCount <- List(1,2,4,8)) {
|
||||
// def parameter = VexRiscvLitexSmpClusterParameter(
|
||||
// cluster = VexRiscvSmpClusterParameter(
|
||||
// cpuConfigs = List.tabulate(cpuCount) { hartId =>
|
||||
// vexRiscvConfig(
|
||||
// hartId = hartId,
|
||||
// ioRange = address => address.msb,
|
||||
// resetVector = 0
|
||||
// )
|
||||
// }
|
||||
// ),
|
||||
// liteDram = LiteDramNativeParameter(addressWidth = 32, dataWidth = 128),
|
||||
// liteDramMapping = SizeMapping(0x40000000l, 0x40000000l)
|
||||
// )
|
||||
//
|
||||
// def dutGen = {
|
||||
// val toplevel = VexRiscvLitexSmpCluster(
|
||||
// p = parameter,
|
||||
// debugClockDomain = ClockDomain.current.copy(reset = Bool().setName("debugResetIn")),
|
||||
// jtagClockDomain = ClockDomain.external("jtag", withReset = false)
|
||||
// )
|
||||
// toplevel
|
||||
// }
|
||||
//
|
||||
// val genConfig = SpinalConfig().addStandardMemBlackboxing(blackboxByteEnables)
|
||||
// // genConfig.generateVerilog(Bench.compressIo(dutGen))
|
||||
// genConfig.generateVerilog(dutGen.setDefinitionName(s"VexRiscvLitexSmpCluster_${cpuCount}c"))
|
||||
// }
|
||||
//
|
||||
//}
|
||||
//
|
||||
//
|
||||
//object VexRiscvLitexSmpClusterOpenSbi extends App{
|
||||
// import spinal.core.sim._
|
||||
//
|
||||
// val simConfig = SimConfig
|
||||
// simConfig.withWave
|
||||
// simConfig.allOptimisation
|
||||
//
|
||||
// val cpuCount = 2
|
||||
//
|
||||
// def parameter = VexRiscvLitexSmpClusterParameter(
|
||||
// cluster = VexRiscvSmpClusterParameter(
|
||||
// cpuConfigs = List.tabulate(cpuCount) { hartId =>
|
||||
// vexRiscvConfig(
|
||||
// hartId = hartId,
|
||||
// ioRange = address => address(31 downto 28) === 0xF,
|
||||
// resetVector = 0x80000000l
|
||||
// )
|
||||
// }
|
||||
// ),
|
||||
// liteDram = LiteDramNativeParameter(addressWidth = 32, dataWidth = 128),
|
||||
// liteDramMapping = SizeMapping(0x80000000l, 0x70000000l)
|
||||
// )
|
||||
//
|
||||
// def dutGen = {
|
||||
// val top = VexRiscvLitexSmpCluster(
|
||||
// p = parameter,
|
||||
// debugClockDomain = ClockDomain.current.copy(reset = Bool().setName("debugResetIn")),
|
||||
// jtagClockDomain = ClockDomain.external("jtag", withReset = false)
|
||||
// )
|
||||
// top.rework{
|
||||
// top.io.clint.setAsDirectionLess.allowDirectionLessIo
|
||||
// top.io.peripheral.setAsDirectionLess.allowDirectionLessIo.simPublic()
|
||||
//
|
||||
// val hit = (top.io.peripheral.ADR <<2 >= 0xF0010000l && top.io.peripheral.ADR<<2 < 0xF0020000l)
|
||||
// top.io.clint.CYC := top.io.peripheral.CYC && hit
|
||||
// top.io.clint.STB := top.io.peripheral.STB
|
||||
// top.io.clint.WE := top.io.peripheral.WE
|
||||
// top.io.clint.ADR := top.io.peripheral.ADR.resized
|
||||
// top.io.clint.DAT_MOSI := top.io.peripheral.DAT_MOSI
|
||||
// top.io.peripheral.DAT_MISO := top.io.clint.DAT_MISO
|
||||
// top.io.peripheral.ACK := top.io.peripheral.CYC && (!hit || top.io.clint.ACK)
|
||||
// top.io.peripheral.ERR := False
|
||||
//
|
||||
object VexRiscvLitexSmpClusterOpenSbi extends App{
|
||||
import spinal.core.sim._
|
||||
|
||||
val simConfig = SimConfig
|
||||
simConfig.withWave
|
||||
simConfig.allOptimisation
|
||||
|
||||
val cpuCount = 2
|
||||
|
||||
def parameter = VexRiscvLitexSmpClusterParameter(
|
||||
cluster = VexRiscvSmpClusterParameter(
|
||||
cpuConfigs = List.tabulate(cpuCount) { hartId =>
|
||||
vexRiscvConfig(
|
||||
hartId = hartId,
|
||||
ioRange = address => address(31 downto 28) === 0xF,
|
||||
resetVector = 0x80000000l
|
||||
)
|
||||
}
|
||||
),
|
||||
liteDram = LiteDramNativeParameter(addressWidth = 32, dataWidth = 128),
|
||||
liteDramMapping = SizeMapping(0x80000000l, 0x70000000l)
|
||||
)
|
||||
|
||||
def dutGen = {
|
||||
val top = new VexRiscvLitexSmpCluster(
|
||||
p = parameter
|
||||
).toComponent()
|
||||
top.rework{
|
||||
top.clintWishbone.setAsDirectionLess.allowDirectionLessIo
|
||||
top.peripheral.setAsDirectionLess.allowDirectionLessIo.simPublic()
|
||||
|
||||
val hit = (top.peripheral.ADR <<2 >= 0xF0010000l && top.peripheral.ADR<<2 < 0xF0020000l)
|
||||
top.clintWishbone.CYC := top.peripheral.CYC && hit
|
||||
top.clintWishbone.STB := top.peripheral.STB
|
||||
top.clintWishbone.WE := top.peripheral.WE
|
||||
top.clintWishbone.ADR := top.peripheral.ADR.resized
|
||||
top.clintWishbone.DAT_MOSI := top.peripheral.DAT_MOSI
|
||||
top.peripheral.DAT_MISO := top.clintWishbone.DAT_MISO
|
||||
top.peripheral.ACK := top.peripheral.CYC && (!hit || top.clintWishbone.ACK)
|
||||
top.peripheral.ERR := False
|
||||
|
||||
// top.dMemBridge.unburstified.cmd.simPublic()
|
||||
// }
|
||||
// top
|
||||
// }
|
||||
// simConfig.compile(dutGen).doSimUntilVoid(seed = 42){dut =>
|
||||
// dut.clockDomain.forkStimulus(10)
|
||||
// fork {
|
||||
// dut.debugClockDomain.resetSim #= false
|
||||
// sleep (0)
|
||||
// dut.debugClockDomain.resetSim #= true
|
||||
// sleep (10)
|
||||
// dut.debugClockDomain.resetSim #= false
|
||||
// }
|
||||
//
|
||||
//
|
||||
// val ram = SparseMemory()
|
||||
// ram.loadBin(0x80000000l, "../opensbi/build/platform/spinal/vexriscv/sim/smp/firmware/fw_jump.bin")
|
||||
// ram.loadBin(0xC0000000l, "../buildroot/output/images/Image")
|
||||
// ram.loadBin(0xC1000000l, "../buildroot/output/images/dtb")
|
||||
// ram.loadBin(0xC2000000l, "../buildroot/output/images/rootfs.cpio")
|
||||
//
|
||||
//
|
||||
// dut.io.iMem.simSlave(ram, dut.clockDomain)
|
||||
// dut.io.dMem.simSlave(ram, dut.clockDomain, dut.dMemBridge.unburstified)
|
||||
//
|
||||
// dut.io.interrupts #= 0
|
||||
//
|
||||
// dut.clockDomain.onFallingEdges{
|
||||
// if(dut.io.peripheral.CYC.toBoolean){
|
||||
// (dut.io.peripheral.ADR.toLong << 2) match {
|
||||
// case 0xF0000000l => print(dut.io.peripheral.DAT_MOSI.toLong.toChar)
|
||||
// case 0xF0000004l => dut.io.peripheral.DAT_MISO #= (if(System.in.available() != 0) System.in.read() else 0xFFFFFFFFl)
|
||||
// case _ =>
|
||||
// }
|
||||
//// println(f"${dut.io.peripheral.ADR.toLong}%x")
|
||||
// }
|
||||
// }
|
||||
//
|
||||
//// fork{
|
||||
//// disableSimWave()
|
||||
//// val atMs = 3790
|
||||
//// val durationMs = 5
|
||||
//// sleep(atMs*1000000l)
|
||||
//// enableSimWave()
|
||||
//// println("** enableSimWave **")
|
||||
//// sleep(durationMs*1000000l)
|
||||
//// println("** disableSimWave **")
|
||||
//// while(true) {
|
||||
//// disableSimWave()
|
||||
//// sleep(100000 * 10)
|
||||
//// enableSimWave()
|
||||
//// sleep( 100 * 10)
|
||||
//// }
|
||||
//// // simSuccess()
|
||||
//// }
|
||||
//
|
||||
// fork{
|
||||
// while(true) {
|
||||
// disableSimWave()
|
||||
// sleep(100000 * 10)
|
||||
// enableSimWave()
|
||||
// sleep( 100 * 10)
|
||||
// }
|
||||
// }
|
||||
// }
|
||||
// }
|
||||
}
|
||||
top
|
||||
}
|
||||
simConfig.compile(dutGen).doSimUntilVoid(seed = 42){dut =>
|
||||
dut.debugCd.inputClockDomain.get.forkStimulus(10)
|
||||
|
||||
val ram = SparseMemory()
|
||||
ram.loadBin(0x80000000l, "../opensbi/build/platform/spinal/vexriscv/sim/smp/firmware/fw_jump.bin")
|
||||
ram.loadBin(0xC0000000l, "../buildroot/output/images/Image")
|
||||
ram.loadBin(0xC1000000l, "../buildroot/output/images/dtb")
|
||||
ram.loadBin(0xC2000000l, "../buildroot/output/images/rootfs.cpio")
|
||||
|
||||
|
||||
dut.iBridge.dram.simSlave(ram, dut.debugCd.inputClockDomain)
|
||||
dut.dBridge.dram.simSlave(ram, dut.debugCd.inputClockDomain/*, dut.dMemBridge.unburstified*/)
|
||||
|
||||
dut.interrupts.get #= 0
|
||||
|
||||
dut.debugCd.inputClockDomain.get.onFallingEdges{
|
||||
if(dut.peripheral.CYC.toBoolean){
|
||||
(dut.peripheral.ADR.toLong << 2) match {
|
||||
case 0xF0000000l => print(dut.peripheral.DAT_MOSI.toLong.toChar)
|
||||
case 0xF0000004l => dut.peripheral.DAT_MISO #= (if(System.in.available() != 0) System.in.read() else 0xFFFFFFFFl)
|
||||
case _ =>
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
fork{
|
||||
while(true) {
|
||||
disableSimWave()
|
||||
sleep(100000 * 10)
|
||||
enableSimWave()
|
||||
sleep( 100 * 10)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue