Fix BrieySim (SpinalSim)

2021-09-25 13:28:37 +02:00 · 2021-09-25 13:28:37 +02:00 · 35754a0709
parent 8c0fbcadac
commit 35754a0709
1 changed files with 2 additions and 0 deletions
--- a/src/main/scala/vexriscv/demo/Briey.scala
+++ b/src/main/scala/vexriscv/demo/Briey.scala
@ -483,6 +483,8 @@ object BrieySim {
        dut.config.sdramLayout,
        clockDomain
      )
+
+      dut.io.coreInterrupt #= false
    }
  }
 }