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Fix BrieySim (SpinalSim)

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Dolu1990 2021-09-25 13:28:37 +02:00
parent 8c0fbcadac
commit 35754a0709
1 changed files with 2 additions and 0 deletions
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2
src/main/scala/vexriscv/demo/Briey.scala
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@ -483,6 +483,8 @@ object BrieySim {
dut.config.sdramLayout,
clockDomain
)
dut.io.coreInterrupt #= false
}
}
}