mirror of
https://github.com/SpinalHDL/VexRiscv.git
synced 2025-01-03 03:43:39 -05:00
Add mdeleg tests
This commit is contained in:
Dolu1990
parent
9139b4d269
commit
3652ede130
15 changed files with 3863 additions and 71 deletions
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@ -833,7 +833,9 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
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execute plug new Area{
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import execute._
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//Manage WFI instructions
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val inWfi = False.addTag(Verilator.public)
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if(wfiGenAsWait) when(arbitration.isValid && input(ENV_CTRL) === EnvCtrlEnum.WFI){
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inWfi := True
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when(!interrupt){
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arbitration.haltItself := True
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}
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@ -1,5 +1,3 @@
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PROJ_NAME=mmu
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RISCV_PATH?=/opt/riscv/
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CFLAGS += -march=rv32i -mabi=ilp32
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4
src/test/cpp/raw/deleg/.gitignore
vendored
Normal file
4
src/test/cpp/raw/deleg/.gitignore
vendored
Normal file
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@ -0,0 +1,4 @@
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*.map
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*.v
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*.elf
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*.o
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399
src/test/cpp/raw/deleg/build/deleg.asm
Normal file
399
src/test/cpp/raw/deleg/build/deleg.asm
Normal file
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@ -0,0 +1,399 @@
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build/deleg.elf: file format elf32-littleriscv
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Disassembly of section .crt_section:
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80000000 <_start>:
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80000000: 00100e93 li t4,1
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80000004: 00000097 auipc ra,0x0
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80000008: 50408093 addi ra,ra,1284 # 80000508 <mtrap>
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8000000c: 30509073 csrw mtvec,ra
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80000010: 00000097 auipc ra,0x0
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80000014: 52c08093 addi ra,ra,1324 # 8000053c <strap>
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80000018: 10509073 csrw stvec,ra
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8000001c: f00110b7 lui ra,0xf0011
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80000020: 00000113 li sp,0
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80000024: 0020a023 sw sp,0(ra) # f0011000 <strap+0x70010ac4>
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80000028 <test1>:
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80000028: 00100e13 li t3,1
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8000002c: 00000f17 auipc t5,0x0
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80000030: 00cf0f13 addi t5,t5,12 # 80000038 <test2>
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80000034: 00000073 ecall
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80000038 <test2>:
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80000038: 00200e13 li t3,2
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8000003c: 000020b7 lui ra,0x2
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80000040: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800>
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80000044: 00000113 li sp,0
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80000048: 3000b073 csrc mstatus,ra
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8000004c: 30012073 csrs mstatus,sp
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80000050: 00000097 auipc ra,0x0
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80000054: 01408093 addi ra,ra,20 # 80000064 <test2+0x2c>
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80000058: 34109073 csrw mepc,ra
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8000005c: 30200073 mret
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80000060: 4900006f j 800004f0 <fail>
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80000064: 00000f17 auipc t5,0x0
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80000068: 024f0f13 addi t5,t5,36 # 80000088 <test4>
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8000006c: 00000073 ecall
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80000070: 4800006f j 800004f0 <fail>
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80000074 <test3>:
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80000074: 00300e13 li t3,3
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80000078: 00000f17 auipc t5,0x0
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8000007c: 010f0f13 addi t5,t5,16 # 80000088 <test4>
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80000080: 00102083 lw ra,1(zero) # 1 <_start-0x7fffffff>
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80000084: 46c0006f j 800004f0 <fail>
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80000088 <test4>:
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80000088: 00400e13 li t3,4
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8000008c: 000020b7 lui ra,0x2
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80000090: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800>
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80000094: 00001137 lui sp,0x1
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80000098: 80010113 addi sp,sp,-2048 # 800 <_start-0x7ffff800>
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8000009c: 3000b073 csrc mstatus,ra
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800000a0: 30012073 csrs mstatus,sp
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800000a4: 00000097 auipc ra,0x0
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800000a8: 01408093 addi ra,ra,20 # 800000b8 <test4+0x30>
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800000ac: 34109073 csrw mepc,ra
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800000b0: 30200073 mret
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800000b4: 43c0006f j 800004f0 <fail>
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800000b8: 00000f17 auipc t5,0x0
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800000bc: 010f0f13 addi t5,t5,16 # 800000c8 <test5>
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800000c0: 00102083 lw ra,1(zero) # 1 <_start-0x7fffffff>
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800000c4: 42c0006f j 800004f0 <fail>
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800000c8 <test5>:
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800000c8: 00500e13 li t3,5
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800000cc: 000020b7 lui ra,0x2
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800000d0: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800>
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800000d4: 00000113 li sp,0
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800000d8: 3000b073 csrc mstatus,ra
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800000dc: 30012073 csrs mstatus,sp
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800000e0: 00000097 auipc ra,0x0
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800000e4: 01408093 addi ra,ra,20 # 800000f4 <test5+0x2c>
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800000e8: 34109073 csrw mepc,ra
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800000ec: 30200073 mret
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800000f0: 4000006f j 800004f0 <fail>
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800000f4: 00000f17 auipc t5,0x0
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800000f8: 010f0f13 addi t5,t5,16 # 80000104 <test6>
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800000fc: 00102083 lw ra,1(zero) # 1 <_start-0x7fffffff>
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80000100: 3f00006f j 800004f0 <fail>
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80000104 <test6>:
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80000104: 00600e13 li t3,6
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80000108: 01000093 li ra,16
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8000010c: 30209073 csrw medeleg,ra
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80000110 <test7>:
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80000110: 00700e13 li t3,7
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80000114: 00000f17 auipc t5,0x0
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80000118: 010f0f13 addi t5,t5,16 # 80000124 <test8>
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8000011c: 00102083 lw ra,1(zero) # 1 <_start-0x7fffffff>
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80000120: 3d00006f j 800004f0 <fail>
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80000124 <test8>:
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80000124: 00800e13 li t3,8
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80000128: 00000f17 auipc t5,0x0
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8000012c: 03cf0f13 addi t5,t5,60 # 80000164 <test9>
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80000130: 000020b7 lui ra,0x2
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80000134: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800>
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80000138: 00001137 lui sp,0x1
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8000013c: 80010113 addi sp,sp,-2048 # 800 <_start-0x7ffff800>
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80000140: 3000b073 csrc mstatus,ra
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80000144: 30012073 csrs mstatus,sp
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80000148: 00000097 auipc ra,0x0
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8000014c: 01408093 addi ra,ra,20 # 8000015c <test8+0x38>
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80000150: 34109073 csrw mepc,ra
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80000154: 30200073 mret
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80000158: 3980006f j 800004f0 <fail>
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8000015c: 00102083 lw ra,1(zero) # 1 <_start-0x7fffffff>
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80000160: 3900006f j 800004f0 <fail>
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80000164 <test9>:
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80000164: 00900e13 li t3,9
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80000168: 00000f17 auipc t5,0x0
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8000016c: 038f0f13 addi t5,t5,56 # 800001a0 <test10>
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80000170: 000020b7 lui ra,0x2
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80000174: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800>
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80000178: 00000113 li sp,0
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8000017c: 3000b073 csrc mstatus,ra
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80000180: 30012073 csrs mstatus,sp
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80000184: 00000097 auipc ra,0x0
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80000188: 01408093 addi ra,ra,20 # 80000198 <test9+0x34>
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8000018c: 34109073 csrw mepc,ra
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80000190: 30200073 mret
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80000194: 35c0006f j 800004f0 <fail>
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80000198: 00102083 lw ra,1(zero) # 1 <_start-0x7fffffff>
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8000019c: 3540006f j 800004f0 <fail>
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800001a0 <test10>:
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800001a0: 00a00e13 li t3,10
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800001a4: 00000f17 auipc t5,0x0
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800001a8: 03cf0f13 addi t5,t5,60 # 800001e0 <test11>
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800001ac: f00110b7 lui ra,0xf0011
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800001b0: 00000113 li sp,0
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800001b4: 0020a023 sw sp,0(ra) # f0011000 <strap+0x70010ac4>
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800001b8: 00800093 li ra,8
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800001bc: 30009073 csrw mstatus,ra
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800001c0: 000010b7 lui ra,0x1
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800001c4: 80008093 addi ra,ra,-2048 # 800 <_start-0x7ffff800>
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800001c8: 30409073 csrw mie,ra
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800001cc: f00110b7 lui ra,0xf0011
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800001d0: 00100113 li sp,1
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800001d4: 0020a023 sw sp,0(ra) # f0011000 <strap+0x70010ac4>
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800001d8: 10500073 wfi
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800001dc: 3140006f j 800004f0 <fail>
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800001e0 <test11>:
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800001e0: 00b00e13 li t3,11
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800001e4: 00000f17 auipc t5,0x0
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800001e8: 068f0f13 addi t5,t5,104 # 8000024c <test12>
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800001ec: f00110b7 lui ra,0xf0011
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800001f0: 00000113 li sp,0
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800001f4: 0020a023 sw sp,0(ra) # f0011000 <strap+0x70010ac4>
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800001f8: 00800093 li ra,8
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800001fc: 30009073 csrw mstatus,ra
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80000200: 000010b7 lui ra,0x1
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80000204: 80008093 addi ra,ra,-2048 # 800 <_start-0x7ffff800>
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80000208: 30409073 csrw mie,ra
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8000020c: 000020b7 lui ra,0x2
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80000210: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800>
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80000214: 00001137 lui sp,0x1
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80000218: 80010113 addi sp,sp,-2048 # 800 <_start-0x7ffff800>
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8000021c: 3000b073 csrc mstatus,ra
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80000220: 30012073 csrs mstatus,sp
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80000224: 00000097 auipc ra,0x0
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80000228: 01408093 addi ra,ra,20 # 80000238 <test11+0x58>
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8000022c: 34109073 csrw mepc,ra
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80000230: 30200073 mret
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80000234: 2bc0006f j 800004f0 <fail>
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80000238: f00110b7 lui ra,0xf0011
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8000023c: 00100113 li sp,1
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80000240: 0020a023 sw sp,0(ra) # f0011000 <strap+0x70010ac4>
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80000244: 10500073 wfi
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80000248: 2a80006f j 800004f0 <fail>
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8000024c <test12>:
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8000024c: 00c00e13 li t3,12
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80000250: 00000f17 auipc t5,0x0
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80000254: 064f0f13 addi t5,t5,100 # 800002b4 <test14>
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80000258: f00110b7 lui ra,0xf0011
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8000025c: 00000113 li sp,0
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80000260: 0020a023 sw sp,0(ra) # f0011000 <strap+0x70010ac4>
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80000264: 00800093 li ra,8
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80000268: 30009073 csrw mstatus,ra
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8000026c: 000010b7 lui ra,0x1
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80000270: 80008093 addi ra,ra,-2048 # 800 <_start-0x7ffff800>
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80000274: 30409073 csrw mie,ra
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80000278: 000020b7 lui ra,0x2
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8000027c: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800>
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80000280: 00000113 li sp,0
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80000284: 3000b073 csrc mstatus,ra
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80000288: 30012073 csrs mstatus,sp
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8000028c: 00000097 auipc ra,0x0
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80000290: 01408093 addi ra,ra,20 # 800002a0 <test12+0x54>
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80000294: 34109073 csrw mepc,ra
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80000298: 30200073 mret
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8000029c: 2540006f j 800004f0 <fail>
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800002a0: f00110b7 lui ra,0xf0011
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800002a4: 00100113 li sp,1
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800002a8: 0020a023 sw sp,0(ra) # f0011000 <strap+0x70010ac4>
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800002ac: 10500073 wfi
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800002b0: 2400006f j 800004f0 <fail>
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800002b4 <test14>:
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800002b4: 00200093 li ra,2
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800002b8: 10009073 csrw sstatus,ra
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800002bc: 00e00e13 li t3,14
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800002c0: 00000f17 auipc t5,0x0
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800002c4: 040f0f13 addi t5,t5,64 # 80000300 <test15>
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800002c8: f00120b7 lui ra,0xf0012
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800002cc: 00000113 li sp,0
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800002d0: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011ac4>
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800002d4: 00200093 li ra,2
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800002d8: 30009073 csrw mstatus,ra
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800002dc: 20000093 li ra,512
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800002e0: 30409073 csrw mie,ra
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800002e4: 00000e93 li t4,0
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800002e8: f00120b7 lui ra,0xf0012
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800002ec: 00100113 li sp,1
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800002f0: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011ac4>
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800002f4: 06400093 li ra,100
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800002f8: fff08093 addi ra,ra,-1
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800002fc: fe104ee3 bgtz ra,800002f8 <test14+0x44>
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80000300 <test15>:
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80000300: 00f00e13 li t3,15
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80000304: 00000f17 auipc t5,0x0
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80000308: 068f0f13 addi t5,t5,104 # 8000036c <test16>
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8000030c: f00120b7 lui ra,0xf0012
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80000310: 00000113 li sp,0
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80000314: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011ac4>
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80000318: 00200093 li ra,2
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8000031c: 30009073 csrw mstatus,ra
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80000320: 20000093 li ra,512
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80000324: 30409073 csrw mie,ra
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80000328: 000020b7 lui ra,0x2
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8000032c: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800>
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80000330: 00001137 lui sp,0x1
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80000334: 80010113 addi sp,sp,-2048 # 800 <_start-0x7ffff800>
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80000338: 3000b073 csrc mstatus,ra
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8000033c: 30012073 csrs mstatus,sp
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80000340: 00000097 auipc ra,0x0
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80000344: 01408093 addi ra,ra,20 # 80000354 <test15+0x54>
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80000348: 34109073 csrw mepc,ra
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8000034c: 30200073 mret
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80000350: 1a00006f j 800004f0 <fail>
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80000354: 00100e93 li t4,1
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80000358: f00120b7 lui ra,0xf0012
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8000035c: 00100113 li sp,1
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80000360: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011ac4>
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80000364: 10500073 wfi
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80000368: 1880006f j 800004f0 <fail>
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8000036c <test16>:
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8000036c: 01000e13 li t3,16
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80000370: 00000f17 auipc t5,0x0
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80000374: 060f0f13 addi t5,t5,96 # 800003d0 <test17>
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80000378: f00120b7 lui ra,0xf0012
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8000037c: 00000113 li sp,0
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80000380: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011ac4>
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80000384: 00200093 li ra,2
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80000388: 30009073 csrw mstatus,ra
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8000038c: 20000093 li ra,512
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80000390: 30409073 csrw mie,ra
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80000394: 000020b7 lui ra,0x2
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80000398: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800>
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8000039c: 00000113 li sp,0
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800003a0: 3000b073 csrc mstatus,ra
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800003a4: 30012073 csrs mstatus,sp
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800003a8: 00000097 auipc ra,0x0
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800003ac: 01408093 addi ra,ra,20 # 800003bc <test16+0x50>
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800003b0: 34109073 csrw mepc,ra
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800003b4: 30200073 mret
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800003b8: 1380006f j 800004f0 <fail>
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800003bc: f00120b7 lui ra,0xf0012
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800003c0: 00100113 li sp,1
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800003c4: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011ac4>
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800003c8: 10500073 wfi
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800003cc: 1240006f j 800004f0 <fail>
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800003d0 <test17>:
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800003d0: 01100e13 li t3,17
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800003d4: 20000093 li ra,512
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800003d8: 30309073 csrw mideleg,ra
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800003dc: 00000f17 auipc t5,0x0
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800003e0: 040f0f13 addi t5,t5,64 # 8000041c <test18>
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800003e4: f00120b7 lui ra,0xf0012
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800003e8: 00000113 li sp,0
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800003ec: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011ac4>
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800003f0: 00200093 li ra,2
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800003f4: 30009073 csrw mstatus,ra
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800003f8: 20000093 li ra,512
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800003fc: 30409073 csrw mie,ra
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80000400: 00000e93 li t4,0
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80000404: f00120b7 lui ra,0xf0012
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80000408: 00100113 li sp,1
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8000040c: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011ac4>
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80000410: 06400093 li ra,100
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80000414: fff08093 addi ra,ra,-1
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80000418: fe104ee3 bgtz ra,80000414 <test17+0x44>
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8000041c <test18>:
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8000041c: 01200e13 li t3,18
|
||||
80000420: 00000f17 auipc t5,0x0
|
||||
80000424: 068f0f13 addi t5,t5,104 # 80000488 <test19>
|
||||
80000428: f00120b7 lui ra,0xf0012
|
||||
8000042c: 00000113 li sp,0
|
||||
80000430: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011ac4>
|
||||
80000434: 00200093 li ra,2
|
||||
80000438: 30009073 csrw mstatus,ra
|
||||
8000043c: 20000093 li ra,512
|
||||
80000440: 30409073 csrw mie,ra
|
||||
80000444: 000020b7 lui ra,0x2
|
||||
80000448: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800>
|
||||
8000044c: 00001137 lui sp,0x1
|
||||
80000450: 80010113 addi sp,sp,-2048 # 800 <_start-0x7ffff800>
|
||||
80000454: 3000b073 csrc mstatus,ra
|
||||
80000458: 30012073 csrs mstatus,sp
|
||||
8000045c: 00000097 auipc ra,0x0
|
||||
80000460: 01408093 addi ra,ra,20 # 80000470 <test18+0x54>
|
||||
80000464: 34109073 csrw mepc,ra
|
||||
80000468: 30200073 mret
|
||||
8000046c: 0840006f j 800004f0 <fail>
|
||||
80000470: 00100e93 li t4,1
|
||||
80000474: f00120b7 lui ra,0xf0012
|
||||
80000478: 00100113 li sp,1
|
||||
8000047c: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011ac4>
|
||||
80000480: 10500073 wfi
|
||||
80000484: 06c0006f j 800004f0 <fail>
|
||||
|
||||
80000488 <test19>:
|
||||
80000488: 01300e13 li t3,19
|
||||
8000048c: 00000f17 auipc t5,0x0
|
||||
80000490: 060f0f13 addi t5,t5,96 # 800004ec <test20>
|
||||
80000494: f00120b7 lui ra,0xf0012
|
||||
80000498: 00000113 li sp,0
|
||||
8000049c: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011ac4>
|
||||
800004a0: 00200093 li ra,2
|
||||
800004a4: 30009073 csrw mstatus,ra
|
||||
800004a8: 20000093 li ra,512
|
||||
800004ac: 30409073 csrw mie,ra
|
||||
800004b0: 000020b7 lui ra,0x2
|
||||
800004b4: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800>
|
||||
800004b8: 00000113 li sp,0
|
||||
800004bc: 3000b073 csrc mstatus,ra
|
||||
800004c0: 30012073 csrs mstatus,sp
|
||||
800004c4: 00000097 auipc ra,0x0
|
||||
800004c8: 01408093 addi ra,ra,20 # 800004d8 <test19+0x50>
|
||||
800004cc: 34109073 csrw mepc,ra
|
||||
800004d0: 30200073 mret
|
||||
800004d4: 01c0006f j 800004f0 <fail>
|
||||
800004d8: f00120b7 lui ra,0xf0012
|
||||
800004dc: 00100113 li sp,1
|
||||
800004e0: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011ac4>
|
||||
800004e4: 10500073 wfi
|
||||
800004e8: 0080006f j 800004f0 <fail>
|
||||
|
||||
800004ec <test20>:
|
||||
800004ec: 0100006f j 800004fc <pass>
|
||||
|
||||
800004f0 <fail>:
|
||||
800004f0: f0100137 lui sp,0xf0100
|
||||
800004f4: f2410113 addi sp,sp,-220 # f00fff24 <strap+0x700ff9e8>
|
||||
800004f8: 01c12023 sw t3,0(sp)
|
||||
|
||||
800004fc <pass>:
|
||||
800004fc: f0100137 lui sp,0xf0100
|
||||
80000500: f2010113 addi sp,sp,-224 # f00fff20 <strap+0x700ff9e4>
|
||||
80000504: 00012023 sw zero,0(sp)
|
||||
|
||||
80000508 <mtrap>:
|
||||
80000508: fe0e84e3 beqz t4,800004f0 <fail>
|
||||
8000050c: 342020f3 csrr ra,mcause
|
||||
80000510: 341020f3 csrr ra,mepc
|
||||
80000514: 300020f3 csrr ra,mstatus
|
||||
80000518: 08000093 li ra,128
|
||||
8000051c: 3000b073 csrc mstatus,ra
|
||||
80000520: 00200093 li ra,2
|
||||
80000524: fc1e8ce3 beq t4,ra,800004fc <pass>
|
||||
80000528: 000020b7 lui ra,0x2
|
||||
8000052c: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800>
|
||||
80000530: 3000a073 csrs mstatus,ra
|
||||
80000534: 341f1073 csrw mepc,t5
|
||||
80000538: 30200073 mret
|
||||
|
||||
8000053c <strap>:
|
||||
8000053c: fa0e8ae3 beqz t4,800004f0 <fail>
|
||||
80000540: 142020f3 csrr ra,scause
|
||||
80000544: 141020f3 csrr ra,sepc
|
||||
80000548: 100020f3 csrr ra,sstatus
|
||||
8000054c: 00000073 ecall
|
||||
80000550: 00000013 nop
|
||||
80000554: 00000013 nop
|
||||
80000558: 00000013 nop
|
||||
8000055c: 00000013 nop
|
||||
80000560: 00000013 nop
|
||||
80000564: 00000013 nop
|
||||
90
src/test/cpp/raw/deleg/build/deleg.hex
Normal file
90
src/test/cpp/raw/deleg/build/deleg.hex
Normal file
|
|
@ -0,0 +1,90 @@
|
|||
:0200000480007A
|
||||
:10000000930E100097000000938040507390503082
|
||||
:10001000970000009380C05273905010B71001F009
|
||||
:100020001301000023A02000130E1000170F000082
|
||||
:10003000130FCF0073000000130E2000B720000044
|
||||
:10004000938000801301000073B0003073200130F2
|
||||
:1000500097000000938040017390103473002030AB
|
||||
:100060006F000049170F0000130F4F0273000000CC
|
||||
:100070006F000048130E3000170F0000130F0F0120
|
||||
:10008000832010006F00C046130E4000B720000010
|
||||
:1000900093800080371100001301018073B000309D
|
||||
:1000A000732001309700000093804001739010345A
|
||||
:1000B000730020306F00C043170F0000130F0F01B3
|
||||
:1000C000832010006F00C042130E5000B7200000C4
|
||||
:1000D000938000801301000073B000307320013062
|
||||
:1000E000970000009380400173901034730020301B
|
||||
:1000F0006F000040170F0000130F0F018320100046
|
||||
:100100006F00003F130E60009300000173902030D9
|
||||
:10011000130E7000170F0000130F0F018320100043
|
||||
:100120006F00003D130E8000170F0000130FCF0368
|
||||
:10013000B720000093800080371100001301018078
|
||||
:1001400073B00030732001309700000093804001AD
|
||||
:1001500073901034730020306F00803983201000BA
|
||||
:100160006F000039130E9000170F0000130F8F035C
|
||||
:10017000B7200000938000801301000073B00030AE
|
||||
:100180007320013097000000938040017390103479
|
||||
:10019000730020306F00C035832010006F004035A1
|
||||
:1001A000130EA000170F0000130FCF03B71001F0BC
|
||||
:1001B0001301000023A02000930080007390003002
|
||||
:1001C000B71000009380008073904030B71001F0AA
|
||||
:1001D0001301100023A02000730050106F00403165
|
||||
:1001E000130EB000170F0000130F8F06B71001F0A9
|
||||
:1001F0001301000023A020009300800073900030C2
|
||||
:10020000B71000009380008073904030B72000004A
|
||||
:1002100093800080371100001301018073B000301B
|
||||
:1002200073200130970000009380400173901034D8
|
||||
:10023000730020306F00C02BB71001F013011000C5
|
||||
:1002400023A02000730050106F00802A130EC000FE
|
||||
:10025000170F0000130F4F06B71001F01301000035
|
||||
:1002600023A020009300800073900030B71000009E
|
||||
:100270009380008073904030B7200000938000800E
|
||||
:100280001301000073B000307320013097000000AC
|
||||
:100290009380400173901034730020306F0040252C
|
||||
:1002A000B71001F01301100023A0200073005010BC
|
||||
:1002B0006F0000249300200073900010130EE000E4
|
||||
:1002C000170F0000130F0F04B72001F013010000F7
|
||||
:1002D00023A02000930020007390003093000020A2
|
||||
:1002E00073904030930E0000B72001F0130110000E
|
||||
:1002F00023A02000930040069380F0FFE34E10FE01
|
||||
:10030000130EF000170F0000130F8F06B72001F037
|
||||
:100310001301000023A02000930020007390003000
|
||||
:100320009300002073904030B7200000938000803D
|
||||
:10033000371100001301018073B0003073200130C9
|
||||
:1003400097000000938040017390103473002030B8
|
||||
:100350006F00001A930E1000B72001F01301100077
|
||||
:1003600023A02000730050106F008018130E0001AE
|
||||
:10037000170F0000130F0F06B72001F01301000044
|
||||
:1003800023A02000930020007390003093000020F1
|
||||
:1003900073904030B720000093800080130100006C
|
||||
:1003A00073B000307320013097000000938040014B
|
||||
:1003B00073901034730020306F008013B72001F069
|
||||
:1003C0001301100023A02000730050106F00401292
|
||||
:1003D000130E10019300002073903030170F0000AF
|
||||
:1003E000130F0F04B72001F01301000023A0200019
|
||||
:1003F00093002000739000309300002073904030F1
|
||||
:10040000930E0000B72001F01301100023A020007C
|
||||
:10041000930040069380F0FFE34E10FE130E200180
|
||||
:10042000170F0000130F8F06B72001F01301000013
|
||||
:1004300023A0200093002000739000309300002040
|
||||
:1004400073904030B7200000938000803711000087
|
||||
:100450001301018073B00030732001309700000059
|
||||
:100460009380400173901034730020306F00400877
|
||||
:10047000930E1000B72001F01301100023A02000FC
|
||||
:10048000730050106F00C006130E3001170F0000EC
|
||||
:10049000130F0F06B72001F01301000023A0200066
|
||||
:1004A0009300200073900030930000207390403040
|
||||
:1004B000B7200000938000801301000073B000306B
|
||||
:1004C0007320013097000000938040017390103436
|
||||
:1004D000730020306F00C001B72001F0130110003D
|
||||
:1004E00023A02000730050106F0080006F000001F7
|
||||
:1004F000370110F0130141F22320C101370110F040
|
||||
:10050000130101F223200100E3840EFEF3202034C6
|
||||
:10051000F3201034F32000309300000873B0003053
|
||||
:1005200093002000E38C1EFCB72000009380008025
|
||||
:1005300073A0003073101F3473002030E38A0EFA6A
|
||||
:10054000F3202014F3201014F32000107300000097
|
||||
:10055000130000001300000013000000130000004F
|
||||
:0805600013000000130000006D
|
||||
:040000058000000077
|
||||
:00000001FF
|
||||
3
src/test/cpp/raw/deleg/makefile
Normal file
3
src/test/cpp/raw/deleg/makefile
Normal file
|
|
@ -0,0 +1,3 @@
|
|||
PROJ_NAME=deleg
|
||||
|
||||
include ../common/asm.mk
|
||||
273
src/test/cpp/raw/deleg/src/crt.S
Normal file
273
src/test/cpp/raw/deleg/src/crt.S
Normal file
|
|
@ -0,0 +1,273 @@
|
|||
.globl _start
|
||||
|
||||
#define TEST_ID x28
|
||||
#define TRAP_OK x29
|
||||
#define TRAP_RET x30
|
||||
|
||||
#include "encoding.h"
|
||||
|
||||
#define externalInterrupt(value) \
|
||||
li x1, 0xF0011000; \
|
||||
li x2, value; \
|
||||
sw x2, 0(x1); \
|
||||
|
||||
#define externalInterruptS(value) \
|
||||
li x1, 0xF0012000; \
|
||||
li x2, value; \
|
||||
sw x2, 0(x1); \
|
||||
|
||||
|
||||
|
||||
#define delay() \
|
||||
li x1, 100; \
|
||||
1: \
|
||||
addi x1, x1, -1; \
|
||||
bgt x1, x0, 1b; \
|
||||
|
||||
|
||||
#define setPriv(value) \
|
||||
li x1, 3 << 11; \
|
||||
li x2, value << 11; \
|
||||
csrc mstatus, x1; \
|
||||
csrs mstatus, x2; \
|
||||
auipc x1, 0; \
|
||||
addi x1, x1, 20; \
|
||||
csrw mepc, x1; \
|
||||
mret; \
|
||||
j fail; \
|
||||
|
||||
|
||||
ROM_SUPER_0:
|
||||
|
||||
_start:
|
||||
li TRAP_OK, 1
|
||||
la x1, mtrap
|
||||
csrw mtvec, x1
|
||||
la x1, strap
|
||||
csrw stvec, x1
|
||||
externalInterrupt(0);
|
||||
|
||||
test1:
|
||||
li TEST_ID, 1
|
||||
la TRAP_RET, test2
|
||||
ecall
|
||||
|
||||
test2: //simple ecall from user to machine
|
||||
li TEST_ID, 2
|
||||
setPriv(0)
|
||||
la TRAP_RET, test4
|
||||
ecall
|
||||
j fail
|
||||
|
||||
test3: //M mialigned load exception without deleg
|
||||
li TEST_ID, 3
|
||||
la TRAP_RET, test4
|
||||
lw x1, 1(x0)
|
||||
j fail
|
||||
test4: //S mialigned load exception without deleg
|
||||
li TEST_ID, 4
|
||||
setPriv(1)
|
||||
la TRAP_RET, test5
|
||||
lw x1, 1(x0)
|
||||
j fail
|
||||
test5: //U mialigned load exception without deleg
|
||||
li TEST_ID, 5
|
||||
setPriv(0)
|
||||
la TRAP_RET, test6
|
||||
lw x1, 1(x0)
|
||||
j fail
|
||||
|
||||
test6: // set medeleg
|
||||
li TEST_ID, 6
|
||||
li x1, 1 << CAUSE_MISALIGNED_LOAD
|
||||
csrw medeleg, x1
|
||||
|
||||
test7: //machine mode exception
|
||||
li TEST_ID, 7
|
||||
la TRAP_RET, test8
|
||||
lw x1, 1(x0)
|
||||
j fail
|
||||
|
||||
test8: //supervisor mode exception
|
||||
li TEST_ID, 8
|
||||
la TRAP_RET, test9
|
||||
setPriv(1)
|
||||
lw x1, 1(x0)
|
||||
j fail
|
||||
|
||||
test9: //user mode exception
|
||||
li TEST_ID, 9
|
||||
la TRAP_RET, test10
|
||||
setPriv(0)
|
||||
lw x1, 1(x0)
|
||||
j fail
|
||||
|
||||
test10: //M external interrupt
|
||||
li TEST_ID, 10
|
||||
la TRAP_RET, test11
|
||||
externalInterrupt(0)
|
||||
li x1, MSTATUS_MIE
|
||||
csrw mstatus, x1
|
||||
li x1, 1 << 11
|
||||
csrw mie, x1
|
||||
externalInterrupt(1)
|
||||
wfi
|
||||
j fail
|
||||
|
||||
test11: //S external interrupt
|
||||
li TEST_ID, 11
|
||||
la TRAP_RET, test12
|
||||
externalInterrupt(0)
|
||||
li x1, MSTATUS_MIE
|
||||
csrw mstatus, x1
|
||||
li x1, 1 << 11
|
||||
csrw mie, x1
|
||||
setPriv(1)
|
||||
externalInterrupt(1)
|
||||
wfi
|
||||
j fail
|
||||
|
||||
test12: //U external interrupt
|
||||
li TEST_ID, 12
|
||||
la TRAP_RET, test14
|
||||
externalInterrupt(0)
|
||||
li x1, MSTATUS_MIE
|
||||
csrw mstatus, x1
|
||||
li x1, 1 << 11
|
||||
csrw mie, x1
|
||||
setPriv(0)
|
||||
externalInterrupt(1)
|
||||
wfi
|
||||
j fail
|
||||
|
||||
|
||||
|
||||
test14: //M external interrupt S
|
||||
li x1, MSTATUS_SIE
|
||||
csrw sstatus, x1
|
||||
|
||||
li TEST_ID, 14
|
||||
la TRAP_RET, test15
|
||||
externalInterruptS(0)
|
||||
li x1, MSTATUS_SIE
|
||||
csrw mstatus, x1
|
||||
li x1, 1 << 9
|
||||
csrw mie, x1
|
||||
li TRAP_OK, 0
|
||||
externalInterruptS(1)
|
||||
delay()
|
||||
|
||||
test15: //S external interrupt S
|
||||
li TEST_ID, 15
|
||||
la TRAP_RET, test16
|
||||
externalInterruptS(0)
|
||||
li x1, SSTATUS_SIE
|
||||
csrw mstatus, x1
|
||||
li x1, 1 << 9
|
||||
csrw mie, x1
|
||||
setPriv(1)
|
||||
li TRAP_OK, 1
|
||||
externalInterruptS(1)
|
||||
wfi
|
||||
j fail
|
||||
|
||||
test16: //U external interrupt S
|
||||
li TEST_ID, 16
|
||||
la TRAP_RET, test17
|
||||
externalInterruptS(0)
|
||||
li x1, SSTATUS_SIE
|
||||
csrw mstatus, x1
|
||||
li x1, 1 << 9
|
||||
csrw mie, x1
|
||||
setPriv(0)
|
||||
externalInterruptS(1)
|
||||
wfi
|
||||
j fail
|
||||
|
||||
|
||||
test17:// set mideleg
|
||||
li TEST_ID, 17
|
||||
li x1, 1 << 9
|
||||
csrw mideleg, x1
|
||||
|
||||
|
||||
la TRAP_RET, test18
|
||||
externalInterruptS(0)
|
||||
li x1, MSTATUS_SIE
|
||||
csrw mstatus, x1
|
||||
li x1, 1 << 9
|
||||
csrw mie, x1
|
||||
li TRAP_OK, 0
|
||||
externalInterruptS(1)
|
||||
delay()
|
||||
|
||||
test18: //S external interrupt S with deleg
|
||||
li TEST_ID, 18
|
||||
la TRAP_RET, test19
|
||||
externalInterruptS(0)
|
||||
li x1, SSTATUS_SIE
|
||||
csrw mstatus, x1
|
||||
li x1, 1 << 9
|
||||
csrw mie, x1
|
||||
setPriv(1)
|
||||
li TRAP_OK, 1
|
||||
externalInterruptS(1)
|
||||
wfi
|
||||
j fail
|
||||
|
||||
test19: //U external interrupt S with deleg
|
||||
li TEST_ID, 19
|
||||
la TRAP_RET, test20
|
||||
externalInterruptS(0)
|
||||
li x1, SSTATUS_SIE
|
||||
csrw mstatus, x1
|
||||
li x1, 1 << 9
|
||||
csrw mie, x1
|
||||
setPriv(0)
|
||||
externalInterruptS(1)
|
||||
wfi
|
||||
j fail
|
||||
|
||||
|
||||
test20:
|
||||
j pass
|
||||
|
||||
fail:
|
||||
li x2, 0xF00FFF24
|
||||
sw TEST_ID, 0(x2)
|
||||
|
||||
pass:
|
||||
li x2, 0xF00FFF20
|
||||
sw x0, 0(x2)
|
||||
|
||||
|
||||
mtrap:
|
||||
beq TRAP_OK, x0, fail
|
||||
csrr x1, mcause
|
||||
csrr x1, mepc
|
||||
csrr x1, mstatus
|
||||
li x1, MSTATUS_MPIE
|
||||
csrc mstatus, x1
|
||||
li x1, 2
|
||||
beq TRAP_OK, x1, pass
|
||||
li x1, 3 << 11
|
||||
csrs mstatus, x1
|
||||
csrw mepc, TRAP_RET
|
||||
mret
|
||||
|
||||
|
||||
strap:
|
||||
beq TRAP_OK, x0, fail
|
||||
csrr x1, scause
|
||||
csrr x1, sepc
|
||||
csrr x1, sstatus
|
||||
ecall
|
||||
|
||||
|
||||
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
1471
src/test/cpp/raw/deleg/src/encoding.h
Normal file
1471
src/test/cpp/raw/deleg/src/encoding.h
Normal file
File diff suppressed because it is too large
Load diff
16
src/test/cpp/raw/deleg/src/ld
Normal file
16
src/test/cpp/raw/deleg/src/ld
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
OUTPUT_ARCH( "riscv" )
|
||||
|
||||
MEMORY {
|
||||
onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 128K
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
.crt_section :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*crt.o(.text)
|
||||
} > onChipRam
|
||||
|
||||
}
|
||||
|
|
@ -435,11 +435,11 @@ Disassembly of section .crt_section:
|
|||
80000594: fe0e80e3 beqz t4,80000574 <failFence>
|
||||
80000598: 342020f3 csrr ra,mcause
|
||||
8000059c: 341020f3 csrr ra,mepc
|
||||
800005a0: 00200093 li ra,2
|
||||
800005a4: fe1e82e3 beq t4,ra,80000588 <passFence>
|
||||
800005a8: 341f1073 csrw mepc,t5
|
||||
800005ac: 30200073 mret
|
||||
800005b0: 00000013 nop
|
||||
800005a0: 300020f3 csrr ra,mstatus
|
||||
800005a4: 00200093 li ra,2
|
||||
800005a8: fe1e80e3 beq t4,ra,80000588 <passFence>
|
||||
800005ac: 341f1073 csrw mepc,t5
|
||||
800005b0: 30200073 mret
|
||||
800005b4: 00000013 nop
|
||||
800005b8: 00000013 nop
|
||||
800005bc: 00000013 nop
|
||||
|
|
|
|||
|
|
@ -89,8 +89,8 @@
|
|||
:1005700073000000370110F0130141F22320C10184
|
||||
:10058000930E200073000000370110F0130101F2F8
|
||||
:1005900023200100E3800EFEF3202034F3201034EA
|
||||
:1005A00093002000E3821EFE73101F34730020307E
|
||||
:1005B00013000000130000001300000013000000EF
|
||||
:1005A000F320003093002000E3801EFE73101F3400
|
||||
:1005B000730020301300000013000000130000003F
|
||||
:1005C00013000000130000001300000013000000DF
|
||||
:1005D00013000000130000001300000013000000CF
|
||||
:1005E00013000000130000001300000013000000BF
|
||||
|
|
@ -3229,6 +3229,5 @@
|
|||
:10C9B0000000000000000000000000000000000077
|
||||
:10C9C0000000000000000000000000000000000067
|
||||
:10C9D0000000000000000000000000000000000057
|
||||
:04C9E0000000000053
|
||||
:040000058000000077
|
||||
:00000001FF
|
||||
|
|
|
|||
|
|
@ -420,6 +420,7 @@ trap:
|
|||
beq TRAP_OK, x0, failFence
|
||||
csrr x1, mcause
|
||||
csrr x1, mepc
|
||||
csrr x1, mstatus
|
||||
li x1, 2
|
||||
beq TRAP_OK, x1, passFence
|
||||
csrw mepc, TRAP_RET
|
||||
|
|
|
|||
1471
src/test/cpp/regression/encoding.h
Normal file
1471
src/test/cpp/regression/encoding.h
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -18,6 +18,7 @@
|
|||
#include <iomanip>
|
||||
#include <queue>
|
||||
#include <time.h>
|
||||
#include "encoding.h"
|
||||
|
||||
using namespace std;
|
||||
|
||||
|
|
@ -220,6 +221,8 @@ public:
|
|||
uint32_t medeleg;
|
||||
uint32_t mideleg;
|
||||
|
||||
uint32_t interrupts;
|
||||
|
||||
union status {
|
||||
uint32_t raw;
|
||||
struct {
|
||||
|
|
@ -350,13 +353,14 @@ public:
|
|||
mbadaddr = 0;
|
||||
mepc = 0;
|
||||
misa = 0; //TODO
|
||||
status.raw = 0;
|
||||
status.mpp = 3;
|
||||
status.spp = 1;
|
||||
privilege = 3;
|
||||
medeleg = 0;
|
||||
mideleg = 0;
|
||||
satp.mode = 0;
|
||||
status.mxr = 0;
|
||||
status.sum = 0;
|
||||
interrupts = 0;
|
||||
}
|
||||
|
||||
virtual void rfWrite(int32_t address, int32_t data) {
|
||||
|
|
@ -369,7 +373,7 @@ public:
|
|||
lastPc = pc;
|
||||
pc = target;
|
||||
} else {
|
||||
exception(0, 0, target);
|
||||
trap(0, 0, target);
|
||||
}
|
||||
}
|
||||
uint32_t mbadaddr, sbadaddr;
|
||||
|
|
@ -406,16 +410,32 @@ public:
|
|||
return false;
|
||||
}
|
||||
|
||||
void exception(bool interrupt,int32_t cause) {
|
||||
exception(interrupt, cause, false, 0);
|
||||
void trap(bool interrupt,int32_t cause) {
|
||||
trap(interrupt, cause, false, 0);
|
||||
}
|
||||
void exception(bool interrupt,int32_t cause, uint32_t value) {
|
||||
exception(interrupt, cause, true, value);
|
||||
void trap(bool interrupt,int32_t cause, uint32_t value) {
|
||||
trap(interrupt, cause, true, value);
|
||||
}
|
||||
void exception(bool interrupt,int32_t cause, bool valueWrite, uint32_t value) {
|
||||
void trap(bool interrupt,int32_t cause, bool valueWrite, uint32_t value) {
|
||||
//Check leguality of the interrupt
|
||||
if(interrupt) {
|
||||
bool hit = false;
|
||||
for(int i = 0;i < 5;i++){
|
||||
if(pendingInterrupts[i] == 1 << cause){
|
||||
hit = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if(!hit){
|
||||
cout << "DUT had trigger an interrupts which wasn't by the REF" << endl;
|
||||
fail();
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t deleg = interrupt ? mideleg : medeleg;
|
||||
uint32_t targetPrivilege = 3;
|
||||
if(deleg & (1 << cause)) targetPrivilege = 1;
|
||||
targetPrivilege = max(targetPrivilege, privilege);
|
||||
Xtvec xtvec = targetPrivilege == 3 ? mtvec : stvec;
|
||||
|
||||
switch(targetPrivilege){
|
||||
|
|
@ -423,8 +443,8 @@ public:
|
|||
if(valueWrite) mbadaddr = value;
|
||||
mcause.interrupt = interrupt;
|
||||
mcause.exceptionCode = cause;
|
||||
status.mie = false;
|
||||
status.mpie = status.mie;
|
||||
status.mie = false;
|
||||
status.mpp = privilege;
|
||||
mepc = pc;
|
||||
break;
|
||||
|
|
@ -432,8 +452,8 @@ public:
|
|||
if(valueWrite) sbadaddr = value;
|
||||
scause.interrupt = interrupt;
|
||||
scause.exceptionCode = cause;
|
||||
status.sie = false;
|
||||
status.spie = status.sie;
|
||||
status.sie = false;
|
||||
status.spp = privilege;
|
||||
sepc = pc;
|
||||
break;
|
||||
|
|
@ -447,7 +467,7 @@ public:
|
|||
}
|
||||
|
||||
void ilegalInstruction(){
|
||||
exception(0, 2);
|
||||
trap(0, 2);
|
||||
}
|
||||
|
||||
virtual void fail() {
|
||||
|
|
@ -467,6 +487,8 @@ public:
|
|||
case MEPC: *value = mepc; break;
|
||||
case MSCRATCH: *value = mscratch; break;
|
||||
case MISA: *value = misa; break;
|
||||
case MEDELEG: *value = medeleg; break;
|
||||
case MIDELEG: *value = mideleg; break;
|
||||
|
||||
case SSTATUS: *value = status.raw & 0xC0133; break;
|
||||
case SIP: *value = ip.raw & 0x333; break;
|
||||
|
|
@ -495,6 +517,8 @@ public:
|
|||
case MEPC: mepc = value; break;
|
||||
case MSCRATCH: mscratch = value; break;
|
||||
case MISA: misa = value; break;
|
||||
case MEDELEG: medeleg = value; break;
|
||||
case MIDELEG: mideleg = value; break;
|
||||
|
||||
case SSTATUS: maskedWrite(status.raw, value,0xC0133); break;
|
||||
case SIP: maskedWrite(ip.raw, value,0x333); break;
|
||||
|
|
@ -514,16 +538,14 @@ public:
|
|||
|
||||
int livenessStep = 0;
|
||||
int livenessInterrupt = 0;
|
||||
virtual void liveness(bool mIntTimer, bool mIntExt){
|
||||
livenessStep++;
|
||||
bool interruptRequest = (ie.mtie && mIntTimer);
|
||||
if(interruptRequest){
|
||||
if(status.mie){
|
||||
livenessInterrupt++;
|
||||
}
|
||||
} else {
|
||||
livenessInterrupt = 0;
|
||||
}
|
||||
uint32_t pendingInterruptsPtr = 0;
|
||||
uint32_t pendingInterrupts[5] = {0,0,0,0,0};
|
||||
virtual void liveness(bool inWfi){
|
||||
uint32_t pendingInterrupt = getPendingInterrupt();
|
||||
pendingInterrupts[pendingInterruptsPtr++] = getPendingInterrupt();
|
||||
if(pendingInterruptsPtr >= 5) pendingInterruptsPtr = 0;
|
||||
if(pendingInterrupt) livenessInterrupt++; else livenessInterrupt = 0;
|
||||
if(!inWfi) livenessStep++; else livenessStep = 0;
|
||||
|
||||
if(livenessStep > 1000){
|
||||
cout << "Liveness step failure" << endl;
|
||||
|
|
@ -534,9 +556,34 @@ public:
|
|||
cout << "Liveness interrupt failure" << endl;
|
||||
fail();
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
uint32_t getPendingInterrupt(){
|
||||
uint32_t mEnabled = status.mie && privilege == 3 || privilege < 3;
|
||||
uint32_t sEnabled = status.sie && privilege == 1 || privilege < 1;
|
||||
|
||||
uint32_t masked = interrupts & ~mideleg & -mEnabled & ie.raw;
|
||||
if (masked == 0)
|
||||
masked = interrupts & mideleg & -sEnabled & ie.raw & 0x333;
|
||||
|
||||
if (masked) {
|
||||
if (masked & (MIP_MEIP | MIP_SEIP))
|
||||
masked &= (MIP_MEIP | MIP_SEIP);
|
||||
// software interrupts have next-highest priority
|
||||
else if (masked & (MIP_MSIP | MIP_SSIP))
|
||||
masked &= (MIP_MSIP | MIP_SSIP);
|
||||
// timer interrupts have next-highest priority
|
||||
else if (masked & (MIP_MTIP | MIP_STIP))
|
||||
masked &= (MIP_MTIP | MIP_STIP);
|
||||
else
|
||||
fail();
|
||||
}
|
||||
|
||||
return masked;
|
||||
}
|
||||
|
||||
|
||||
bool isPcAligned(uint32_t pc){
|
||||
#ifdef COMPRESSED
|
||||
return (pc & 1) == 0;
|
||||
|
|
@ -579,25 +626,25 @@ public:
|
|||
uint32_t u32Buf;
|
||||
uint32_t pAddr;
|
||||
if (pc & 2) {
|
||||
if(v2p(pc - 2, &pAddr, EXECUTE)){ exception(0, 12); return; }
|
||||
if(v2p(pc - 2, &pAddr, EXECUTE)){ trap(0, 12); return; }
|
||||
if(iRead(pAddr, &i)){
|
||||
exception(0, 1);
|
||||
trap(0, 1);
|
||||
return;
|
||||
}
|
||||
i >>= 16;
|
||||
if (i & 3 == 3) {
|
||||
uint32_t u32Buf;
|
||||
if(v2p(pc + 2, &pAddr, EXECUTE)){ exception(0, 12); return; }
|
||||
if(v2p(pc + 2, &pAddr, EXECUTE)){ trap(0, 12); return; }
|
||||
if(iRead(pAddr, &u32Buf)){
|
||||
exception(0, 1);
|
||||
trap(0, 1);
|
||||
return;
|
||||
}
|
||||
i |= u32Buf << 16;
|
||||
}
|
||||
} else {
|
||||
if(v2p(pc, &pAddr, EXECUTE)){ exception(0, 12); return; }
|
||||
if(v2p(pc, &pAddr, EXECUTE)){ trap(0, 12); return; }
|
||||
if(iRead(pAddr, &i)){
|
||||
exception(0, 1);
|
||||
trap(0, 1);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
|
@ -627,11 +674,11 @@ public:
|
|||
uint32_t address = i32_rs1 + i32_i_imm;
|
||||
uint32_t size = 1 << ((i >> 12) & 0x3);
|
||||
if(address & (size-1)){
|
||||
exception(0, 4, address);
|
||||
trap(0, 4, address);
|
||||
} else {
|
||||
if(v2p(address, &pAddr, READ)){ exception(0, 13); return; }
|
||||
if(v2p(address, &pAddr, READ)){ trap(0, 13); return; }
|
||||
if(dRead(pAddr, size, &data)){
|
||||
exception(0, 5, address);
|
||||
trap(0, 5, address);
|
||||
} else {
|
||||
switch ((i >> 12) & 0x7) {
|
||||
case 0x0:rfWrite(rd32, int8_t(data));pcWrite(pc + 4);break;
|
||||
|
|
@ -647,9 +694,9 @@ public:
|
|||
uint32_t address = i32_rs1 + i32_s_imm;
|
||||
uint32_t size = 1 << ((i >> 12) & 0x3);
|
||||
if(address & (size-1)){
|
||||
exception(0, 6, address);
|
||||
trap(0, 6, address);
|
||||
} else {
|
||||
if(v2p(address, &pAddr, WRITE)){ exception(0, 15); return; }
|
||||
if(v2p(address, &pAddr, WRITE)){ trap(0, 15); return; }
|
||||
dWrite(pAddr, size, i32_rs2);
|
||||
pcWrite(pc + 4);
|
||||
}
|
||||
|
|
@ -730,7 +777,7 @@ public:
|
|||
pcWrite(sepc);
|
||||
}break;
|
||||
case 0x00000073:{ //ECALL
|
||||
exception(0, 8+privilege);
|
||||
trap(0, 8+privilege);
|
||||
}break;
|
||||
case 0x10500073:{ //WFI
|
||||
pcWrite(pc + 4);
|
||||
|
|
@ -771,11 +818,11 @@ public:
|
|||
uint32_t data;
|
||||
uint32_t address = i16_rf1 + i16_lw_imm;
|
||||
if(address & 0x3){
|
||||
exception(0, 4, address);
|
||||
trap(0, 4, address);
|
||||
} else {
|
||||
if(v2p(address, &pAddr, READ)){ exception(0, 13); return; }
|
||||
if(v2p(address, &pAddr, READ)){ trap(0, 13); return; }
|
||||
if(dRead(address, 4, &data)) {
|
||||
exception(1, 5, address);
|
||||
trap(1, 5, address);
|
||||
} else {
|
||||
rfWrite(i16_addr2, data); pcWrite(pc + 2);
|
||||
}
|
||||
|
|
@ -784,9 +831,9 @@ public:
|
|||
case 6: {
|
||||
uint32_t address = i16_rf1 + i16_lw_imm;
|
||||
if(address & 0x3){
|
||||
exception(0, 6, address);
|
||||
trap(0, 6, address);
|
||||
} else {
|
||||
if(v2p(address, &pAddr, WRITE)){ exception(0, 15); return; }
|
||||
if(v2p(address, &pAddr, WRITE)){ trap(0, 15); return; }
|
||||
dWrite(pAddr, 4, i16_rf2);
|
||||
pcWrite(pc + 2);
|
||||
}
|
||||
|
|
@ -820,11 +867,11 @@ public:
|
|||
uint32_t data;
|
||||
uint32_t address = rf_sp + i16_lwsp_imm;
|
||||
if(address & 0x3){
|
||||
exception(0, 4, address);
|
||||
trap(0, 4, address);
|
||||
} else {
|
||||
if(v2p(address, &pAddr, READ)){ exception(0, 13); return; }
|
||||
if(v2p(address, &pAddr, READ)){ trap(0, 13); return; }
|
||||
if(dRead(pAddr, 4, &data)){
|
||||
exception(1, 5, address);
|
||||
trap(1, 5, address);
|
||||
} else {
|
||||
rfWrite(rd32, data); pcWrite(pc + 2);
|
||||
}
|
||||
|
|
@ -850,9 +897,9 @@ public:
|
|||
case 22: {
|
||||
uint32_t address = rf_sp + i16_swsp_imm;
|
||||
if(address & 3){
|
||||
exception(0,6, address);
|
||||
trap(0,6, address);
|
||||
} else {
|
||||
if(v2p(address, &pAddr, WRITE)){ exception(0, 15); return; }
|
||||
if(v2p(address, &pAddr, WRITE)){ trap(0, 15); return; }
|
||||
dWrite(pAddr, 4, regs[iBits(2,5)]); pcWrite(pc + 2);
|
||||
}
|
||||
}break;
|
||||
|
|
@ -1112,6 +1159,13 @@ public:
|
|||
logTraces << (char)mem[0xF0010000u];
|
||||
break;
|
||||
}
|
||||
#ifdef EXTERNAL_INTERRUPT
|
||||
case 0xF0011000u: top->externalInterrupt = *data & 1; break;
|
||||
#endif
|
||||
|
||||
#ifdef SUPERVISOR
|
||||
case 0xF0012000u: top->externalInterruptS = *data & 1; break;
|
||||
#endif
|
||||
case 0xF00FFF00u: {
|
||||
cout << mem[0xF00FFF00u];
|
||||
logTraces << (char)mem[0xF00FFF00u];
|
||||
|
|
@ -1222,6 +1276,9 @@ public:
|
|||
top->timerInterrupt = 0;
|
||||
top->externalInterrupt = 1;
|
||||
#endif
|
||||
#ifdef SUPERVISOR
|
||||
top->externalInterruptS = 0;
|
||||
#endif
|
||||
#ifdef DEBUG_PLUGIN_EXTERNAL
|
||||
top->timerInterrupt = 0;
|
||||
top->externalInterrupt = 0;
|
||||
|
|
@ -1300,8 +1357,21 @@ public:
|
|||
top->eval();
|
||||
|
||||
#ifdef CSR
|
||||
riscvRef.interrupts = 0;
|
||||
#ifdef TIMER_INTERRUPT
|
||||
riscvRef.interrupts |= top->timerInterrupt << 7;
|
||||
#endif
|
||||
#ifdef EXTERNAL_INTERRUPT
|
||||
riscvRef.interrupts |= top->externalInterrupt << 11;
|
||||
#endif
|
||||
#ifdef SUPERVISOR
|
||||
riscvRef.interrupts |= top->timerInterruptS << 5;
|
||||
riscvRef.interrupts |= top->externalInterruptS << 9;
|
||||
#endif
|
||||
|
||||
riscvRef.liveness(top->VexRiscv->execute_CsrPlugin_inWfi);
|
||||
if(top->VexRiscv->CsrPlugin_interruptJump){
|
||||
if(riscvRefEnable) riscvRef.exception(true, top->VexRiscv->CsrPlugin_interruptCode);
|
||||
if(riscvRefEnable) riscvRef.trap(true, top->VexRiscv->CsrPlugin_interruptCode);
|
||||
}
|
||||
#endif
|
||||
if(top->VexRiscv->writeBack_arbitration_isFiring){
|
||||
|
|
@ -1309,16 +1379,6 @@ public:
|
|||
riscvRef.step();
|
||||
bool mIntTimer = false;
|
||||
bool mIntExt = false;
|
||||
|
||||
#ifdef TIMER_INTERRUPT
|
||||
mIntTimer = top->timerInterrupt;
|
||||
#endif
|
||||
#ifdef EXTERNAL_INTERRUPT
|
||||
mIntExt = top->externalInterrupt;
|
||||
#endif
|
||||
|
||||
|
||||
riscvRef.liveness(mIntTimer, mIntExt);
|
||||
}
|
||||
|
||||
if(riscvRefEnable && top->VexRiscv->writeBack_PC != riscvRef.lastPc){
|
||||
|
|
@ -1353,11 +1413,9 @@ public:
|
|||
}
|
||||
if(riscvRefEnable) if(rfWriteValid != riscvRef.rfWriteValid ||
|
||||
(rfWriteValid && (rfWriteAddress!= riscvRef.rfWriteAddress || rfWriteData!= riscvRef.rfWriteData))){
|
||||
cout << "regFile write missmatch ";
|
||||
if(rfWriteValid) cout << "REF: RF[" << riscvRef.rfWriteAddress << "] = 0x" << hex << riscvRef.rfWriteData << dec << " ";
|
||||
if(rfWriteValid) cout << "RTL: RF[" << rfWriteAddress << "] = 0x" << hex << rfWriteData << dec << " ";
|
||||
|
||||
cout << endl;
|
||||
cout << "regFile write missmatch :" << endl;
|
||||
if(rfWriteValid) cout << " REF: RF[" << riscvRef.rfWriteAddress << "] = 0x" << hex << riscvRef.rfWriteData << dec << endl;
|
||||
if(rfWriteValid) cout << " RTL: RF[" << rfWriteAddress << "] = 0x" << hex << rfWriteData << dec << endl;
|
||||
fail();
|
||||
}
|
||||
}
|
||||
|
|
@ -2966,6 +3024,7 @@ int main(int argc, char **argv, char **env) {
|
|||
// #ifdef MMU
|
||||
// redo(REDO,Workspace("mmu").withRiscvRef()->loadHex("../raw/mmu/build/mmu.hex")->bootAt(0x80000000u)->run(50e3););
|
||||
// #endif
|
||||
// redo(REDO,Workspace("deleg").withRiscvRef()->loadHex("../raw/deleg/build/deleg.hex")->bootAt(0x80000000u)->run(50e3););
|
||||
// return 0;
|
||||
|
||||
for(int idx = 0;idx < 1;idx++){
|
||||
|
|
@ -3073,6 +3132,9 @@ int main(int argc, char **argv, char **env) {
|
|||
#ifdef MMU
|
||||
redo(REDO,Workspace("mmu").withRiscvRef()->loadHex("../raw/mmu/build/mmu.hex")->bootAt(0x80000000u)->run(50e3););
|
||||
#endif
|
||||
#ifdef SUPERVISOR
|
||||
redo(REDO,Workspace("deleg").withRiscvRef()->loadHex("../raw/deleg/build/deleg.hex")->bootAt(0x80000000u)->run(50e3););
|
||||
#endif
|
||||
|
||||
#ifdef DEBUG_PLUGIN
|
||||
redo(REDO,DebugPluginTest().run(1e6););
|
||||
|
|
|
|||
|
|
@ -30,6 +30,7 @@ REF_TIME=no
|
|||
THREAD_COUNT?=4
|
||||
MTIME_INSTR_FACTOR?=no
|
||||
COMPRESSED?=no
|
||||
SUPERVISOR?=no
|
||||
STOP_ON_ERROR?=no
|
||||
|
||||
|
||||
|
|
@ -67,7 +68,9 @@ endif
|
|||
ifeq ($(COMPRESSED),yes)
|
||||
ADDCFLAGS += -CFLAGS -DCOMPRESSED
|
||||
endif
|
||||
|
||||
ifeq ($(SUPERVISOR),yes)
|
||||
ADDCFLAGS += -CFLAGS -DSUPERVISOR
|
||||
endif
|
||||
ifeq ($(FENCEI),yes)
|
||||
ADDCFLAGS += -CFLAGS -DFENCEI
|
||||
endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue