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VexRiscv
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Fix Bmb compilation

This commit is contained in:
Charles Papon 2019-05-13 23:44:20 +02:00
parent 8201cff7ff
commit 3753f64429
3 changed files with 89 additions and 23 deletions
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2
src/main/scala/vexriscv/demo/MuraxUtiles.scala
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@ -12,7 +12,7 @@ import vexriscv.plugin.{DBusSimpleBus, IBusSimpleBus}
class MuraxMasterArbiter(pipelinedMemoryBusConfig : PipelinedMemoryBusConfig) extends Component{
val io = new Bundle{
val iBus = slave(IBusSimpleBus(false))
val iBus = slave(IBusSimpleBus(null))
val dBus = slave(DBusSimpleBus())
val masterBus = master(PipelinedMemoryBus(pipelinedMemoryBusConfig))
}

39
src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
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@ -6,6 +6,7 @@ import spinal.lib._
import spinal.lib.bus.amba3.ahblite.{AhbLite3Config, AhbLite3Master}
import spinal.lib.bus.amba4.axi._
import spinal.lib.bus.avalon.{AvalonMM, AvalonMMConfig}
import spinal.lib.bus.bmb.{Bmb, BmbParameter}
import spinal.lib.bus.wishbone.{Wishbone, WishboneConfig}
import spinal.lib.bus.simple._
import vexriscv.ip.DataCacheMemCmd
@ -76,6 +77,18 @@ object DBusSimpleBus{
addressWidth = 32,
dataWidth = 32
)
def getBmbParameter() = BmbParameter(
addressWidth = 32,
dataWidth = 32,
lengthWidth = 2,
sourceWidth = 0,
contextWidth = 1,
canRead = true,
canWrite = true,
allowUnalignedWordBurst = false,
allowUnalignedByteBurst = false,
maximumPendingTransactionPerId = Int.MaxValue
)
}
case class DBusSimpleBus() extends Bundle with IMasterSlave{
@ -208,8 +221,6 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{
bus
}
def toAhbLite3Master(avoidWriteToReadHazard : Boolean): AhbLite3Master = {
val bus = AhbLite3Master(DBusSimpleBus.getAhbLite3Config())
bus.HADDR := this.cmd.address
@ -235,6 +246,30 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{
this.cmd.ready := False
}
}
bus
}
def toBmb() : Bmb = {
val pipelinedMemoryBusConfig = DBusSimpleBus.getBmbParameter()
val bus = Bmb(pipelinedMemoryBusConfig)
bus.cmd.valid := cmd.valid
bus.cmd.last := True
bus.cmd.context(0) := cmd.wr
bus.cmd.opcode := (cmd.wr ? B(Bmb.Cmd.Opcode.WRITE) | B(Bmb.Cmd.Opcode.READ))
bus.cmd.address := cmd.address.resized
bus.cmd.data := cmd.data
bus.cmd.mask := cmd.size.mux(
0 -> B"0001",
1 -> B"0011",
default -> B"1111"
) |<< cmd.address(1 downto 0)
cmd.ready := bus.cmd.ready
rsp.ready := bus.rsp.valid && !bus.rsp.context(0)
rsp.data := bus.rsp.data
rsp.error := bus.rsp.isError
bus.rsp.ready := True
bus
}

71
src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
View File

@ -6,6 +6,7 @@ import spinal.lib._
import spinal.lib.bus.amba3.ahblite.{AhbLite3, AhbLite3Config, AhbLite3Master}
import spinal.lib.bus.amba4.axi._
import spinal.lib.bus.avalon.{AvalonMM, AvalonMMConfig}
import spinal.lib.bus.bmb.{Bmb, BmbParameter}
import spinal.lib.bus.wishbone.{Wishbone, WishboneConfig}
import spinal.lib.bus.simple._
import vexriscv.Riscv.{FENCE, FENCE_I}
@ -67,14 +68,28 @@ object IBusSimpleBus{
dataWidth = 32
)
def getAhbLite3Config() = AhbLite3Config(
addressWidth = 32,
dataWidth = 32
)
def getBmbParameter(plugin : IBusSimplePlugin = null) = BmbParameter(
addressWidth = 32,
dataWidth = 32,
lengthWidth = 2,
sourceWidth = 0,
contextWidth = 0,
canRead = true,
canWrite = false,
allowUnalignedWordBurst = false,
allowUnalignedByteBurst = false,
maximumPendingTransactionPerId = if(plugin != null) plugin.pendingMax else Int.MaxValue
)
}
case class IBusSimpleBus(cmdIsPersistente : Boolean = false) extends Bundle with IMasterSlave {
case class IBusSimpleBus(plugin: IBusSimplePlugin) extends Bundle with IMasterSlave {
var cmd = Stream(IBusSimpleCmd())
var rsp = Flow(IBusSimpleRsp())
@ -85,7 +100,7 @@ case class IBusSimpleBus(cmdIsPersistente : Boolean = false) extends Bundle with
def cmdS2mPipe() : IBusSimpleBus = {
val s = IBusSimpleBus()
val s = IBusSimpleBus(plugin)
s.cmd << this.cmd.s2mPipe()
this.rsp << s.rsp
s
@ -93,7 +108,7 @@ case class IBusSimpleBus(cmdIsPersistente : Boolean = false) extends Bundle with
def toAxi4ReadOnly(): Axi4ReadOnly = {
assert(cmdIsPersistente)
assert(plugin.cmdForkPersistence)
val axi = Axi4ReadOnly(IBusSimpleBus.getAxi4Config())
axi.ar.valid := cmd.valid
@ -112,7 +127,7 @@ case class IBusSimpleBus(cmdIsPersistente : Boolean = false) extends Bundle with
}
def toAvalon(): AvalonMM = {
assert(cmdIsPersistente)
assert(plugin.cmdForkPersistence)
val avalonConfig = IBusSimpleBus.getAvalonConfig()
val mm = AvalonMM(avalonConfig)
@ -163,6 +178,7 @@ case class IBusSimpleBus(cmdIsPersistente : Boolean = false) extends Bundle with
bus
}
//cmdForkPersistence need to bet set
def toAhbLite3Master(): AhbLite3Master = {
val bus = AhbLite3Master(IBusSimpleBus.getAhbLite3Config())
@ -182,6 +198,21 @@ case class IBusSimpleBus(cmdIsPersistente : Boolean = false) extends Bundle with
this.rsp.error := bus.HRESP
bus
}
def toBmb() : Bmb = {
val pipelinedMemoryBusConfig = IBusSimpleBus.getBmbParameter(plugin)
val bus = Bmb(pipelinedMemoryBusConfig)
bus.cmd.arbitrationFrom(cmd)
bus.cmd.opcode := Bmb.Cmd.Opcode.READ
bus.cmd.address := cmd.pc.resized
bus.cmd.length := 3
bus.cmd.last := True
rsp.valid := bus.rsp.valid
rsp.inst := bus.rsp.data
rsp.error := bus.rsp.isError
bus.rsp.ready := True
bus
}
}
@ -189,21 +220,21 @@ case class IBusSimpleBus(cmdIsPersistente : Boolean = false) extends Bundle with
class IBusSimplePlugin(resetVector : BigInt,
cmdForkOnSecondStage : Boolean,
cmdForkPersistence : Boolean,
catchAccessFault : Boolean = false,
prediction : BranchPrediction = NONE,
historyRamSizeLog2 : Int = 10,
keepPcPlus4 : Boolean = false,
compressedGen : Boolean = false,
busLatencyMin : Int = 1,
pendingMax : Int = 7,
injectorStage : Boolean = true,
rspHoldValue : Boolean = false,
singleInstructionPipeline : Boolean = false,
memoryTranslatorPortConfig : Any = null,
relaxPredictorAddress : Boolean = true
class IBusSimplePlugin( resetVector : BigInt,
val cmdForkOnSecondStage : Boolean,
val cmdForkPersistence : Boolean,
val catchAccessFault : Boolean = false,
prediction : BranchPrediction = NONE,
historyRamSizeLog2 : Int = 10,
keepPcPlus4 : Boolean = false,
compressedGen : Boolean = false,
val busLatencyMin : Int = 1,
val pendingMax : Int = 7,
injectorStage : Boolean = true,
val rspHoldValue : Boolean = false,
val singleInstructionPipeline : Boolean = false,
val memoryTranslatorPortConfig : Any = null,
relaxPredictorAddress : Boolean = true
) extends IBusFetcherImpl(
resetVector = resetVector,
keepPcPlus4 = keepPcPlus4,
@ -227,7 +258,7 @@ class IBusSimplePlugin(resetVector : BigInt,
override def setup(pipeline: VexRiscv): Unit = {
super.setup(pipeline)
iBus = master(IBusSimpleBus(cmdForkPersistence)).setName("iBus")
iBus = master(IBusSimpleBus(this)).setName("iBus")
val decoderService = pipeline.service(classOf[DecoderService])
decoderService.add(FENCE_I, Nil)