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SynthesisBench cleaning/experiments

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Dolu1990 2018-02-11 14:53:42 +01:00
parent 2a336c2812
commit 3853e0313b
1 changed files with 35 additions and 12 deletions
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47
src/main/scala/vexriscv/demo/SynthesisBench.scala
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@ -1,62 +1,85 @@
package vexriscv.demo package vexriscv.demo
import spinal.core.SpinalVerilog import spinal.core._
import spinal.lib.eda.bench.{XilinxStdTargets, Bench, AlteraStdTargets, Rtl} import spinal.lib.eda.bench._
import scala.collection.mutable.ArrayBuffer
/** /**
* Created by PIC32F_USER on 16/07/2017. * Created by PIC32F_USER on 16/07/2017.
*/ */
object VexRiscvSynthesisBench { object VexRiscvSynthesisBench {
def main(args: Array[String]) { def main(args: Array[String]) {
def wrap(that : => Component) : Component = that
//Wrap with input/output registers
// def wrap(that : => Component) : Component = {
// //new WrapWithReg.Wrapper(that)
// val c = that
// c.rework {
// for (e <- c.getOrdredNodeIo) {
// if (e.isInput) {
// e.asDirectionLess()
// e := RegNext(RegNext(in(cloneOf(e))))
//
// } else {
// e.asDirectionLess()
// out(cloneOf(e)) := RegNext(RegNext(e))
// }
// }
// }
// c
// }
val smallestNoCsr = new Rtl { val smallestNoCsr = new Rtl {
override def getName(): String = "VexRiscv smallest no CSR" override def getName(): String = "VexRiscv smallest no CSR"
override def getRtlPath(): String = "VexRiscvSmallestNoCsr.v" override def getRtlPath(): String = "VexRiscvSmallestNoCsr.v"
SpinalVerilog(GenSmallestNoCsr.cpu().setDefinitionName(getRtlPath().split("\\.").head)) SpinalVerilog(wrap(GenSmallestNoCsr.cpu()).setDefinitionName(getRtlPath().split("\\.").head))
} }
val smallest = new Rtl { val smallest = new Rtl {
override def getName(): String = "VexRiscv smallest" override def getName(): String = "VexRiscv smallest"
override def getRtlPath(): String = "VexRiscvSmallest.v" override def getRtlPath(): String = "VexRiscvSmallest.v"
SpinalVerilog(GenSmallest.cpu().setDefinitionName(getRtlPath().split("\\.").head)) SpinalVerilog(wrap(GenSmallest.cpu()).setDefinitionName(getRtlPath().split("\\.").head))
} }
val smallAndProductive = new Rtl { val smallAndProductive = new Rtl {
override def getName(): String = "VexRiscv small and productive" override def getName(): String = "VexRiscv small and productive"
override def getRtlPath(): String = "VexRiscvSmallAndProductive.v" override def getRtlPath(): String = "VexRiscvSmallAndProductive.v"
SpinalVerilog(GenSmallAndProductive.cpu().setDefinitionName(getRtlPath().split("\\.").head)) SpinalVerilog(wrap(GenSmallAndProductive.cpu()).setDefinitionName(getRtlPath().split("\\.").head))
} }
val fullNoMmuNoCache = new Rtl { val fullNoMmuNoCache = new Rtl {
override def getName(): String = "VexRiscv full no MMU no cache" override def getName(): String = "VexRiscv full no MMU no cache"
override def getRtlPath(): String = "VexRiscvFullNoMmuNoCache.v" override def getRtlPath(): String = "VexRiscvFullNoMmuNoCache.v"
SpinalVerilog(GenFullNoMmuNoCache.cpu().setDefinitionName(getRtlPath().split("\\.").head)) SpinalVerilog(wrap(GenFullNoMmuNoCache.cpu()).setDefinitionName(getRtlPath().split("\\.").head))
} }
val fullNoMmu = new Rtl { val fullNoMmu = new Rtl {
override def getName(): String = "VexRiscv full no MMU" override def getName(): String = "VexRiscv full no MMU"
override def getRtlPath(): String = "VexRiscvFullNoMmu.v" override def getRtlPath(): String = "VexRiscvFullNoMmu.v"
SpinalVerilog(GenFullNoMmu.cpu().setDefinitionName(getRtlPath().split("\\.").head)) SpinalVerilog(wrap(GenFullNoMmu.cpu()).setDefinitionName(getRtlPath().split("\\.").head))
} }
val noCacheNoMmuMaxPerf= new Rtl { val noCacheNoMmuMaxPerf= new Rtl {
override def getName(): String = "VexRiscv no cache no MMU max perf" override def getName(): String = "VexRiscv no cache no MMU max perf"
override def getRtlPath(): String = "VexRiscvNoCacheNoMmuMaxPerf.v" override def getRtlPath(): String = "VexRiscvNoCacheNoMmuMaxPerf.v"
SpinalVerilog(GenNoCacheNoMmuMaxPerf.cpu().setDefinitionName(getRtlPath().split("\\.").head)) SpinalVerilog(wrap(GenNoCacheNoMmuMaxPerf.cpu()).setDefinitionName(getRtlPath().split("\\.").head))
} }
val fullNoMmuMaxPerf= new Rtl { val fullNoMmuMaxPerf= new Rtl {
override def getName(): String = "VexRiscv full no MMU max perf" override def getName(): String = "VexRiscv full no MMU max perf"
override def getRtlPath(): String = "VexRiscvFullNoMmuMaxPerf.v" override def getRtlPath(): String = "VexRiscvFullNoMmuMaxPerf.v"
SpinalVerilog(GenFullNoMmuMaxPerf.cpu().setDefinitionName(getRtlPath().split("\\.").head)) SpinalVerilog(wrap(GenFullNoMmuMaxPerf.cpu()).setDefinitionName(getRtlPath().split("\\.").head))
} }
val full = new Rtl { val full = new Rtl {
override def getName(): String = "VexRiscv full" override def getName(): String = "VexRiscv full"
override def getRtlPath(): String = "VexRiscvFull.v" override def getRtlPath(): String = "VexRiscvFull.v"
SpinalVerilog(GenFull.cpu().setDefinitionName(getRtlPath().split("\\.").head)) SpinalVerilog(wrap(GenFull.cpu()).setDefinitionName(getRtlPath().split("\\.").head))
} }
// val rtls = List(smallestNoCsr, smallest, smallAndProductive, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full) val rtls = List(smallestNoCsr, smallest, smallAndProductive, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full)
val rtls = List(noCacheNoMmuMaxPerf, fullNoMmuMaxPerf) // val rtls = List(noCacheNoMmuMaxPerf, fullNoMmuMaxPerf)
val targets = XilinxStdTargets( val targets = XilinxStdTargets(
vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin" vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin"