Merge remote-tracking branch 'origin/dev' into smp
This commit is contained in:
Dolu1990
commit
3885e52bb7
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@ -417,10 +417,10 @@ A prebuild GCC toolsuite can be found here:
|
||||||
The VexRiscvSocSoftware makefiles are expecting to find this prebuild version in /opt/riscv/__contentOfThisPreBuild__
|
The VexRiscvSocSoftware makefiles are expecting to find this prebuild version in /opt/riscv/__contentOfThisPreBuild__
|
||||||
|
|
||||||
```sh
|
```sh
|
||||||
wget https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-20171231-x86_64-linux-centos6.tar.gz
|
version=riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-ubuntu14
|
||||||
tar -xzvf riscv64-unknown-elf-gcc-20171231-x86_64-linux-centos6.tar.gz
|
wget -O riscv64-unknown-elf-gcc.tar.gz riscv https://static.dev.sifive.com/dev-tools/$version.tar.gz
|
||||||
sudo mv riscv64-unknown-elf-gcc-20171231-x86_64-linux-centos6 /opt/riscv64-unknown-elf-gcc-20171231-x86_64-linux-centos6
|
tar -xzvf riscv64-unknown-elf-gcc.tar.gz
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||||||
sudo mv /opt/riscv64-unknown-elf-gcc-20171231-x86_64-linux-centos6 /opt/riscv
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sudo mv $version /opt/riscv
|
||||||
echo 'export PATH=/opt/riscv/bin:$PATH' >> ~/.bashrc
|
echo 'export PATH=/opt/riscv/bin:$PATH' >> ~/.bashrc
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||||||
```
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```
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||||||
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||||||
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||||||
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@ -1,241 +0,0 @@
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||||||
package spinal.lib.bus.wishbone
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||||||
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||||||
import spinal.core._
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import spinal.lib._
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/** This class is used for configuring the Wishbone class
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* @param addressWidth size in bits of the address line
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* @param dataWidth size in bits of the data line
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||||||
* @param selWidth size in bits of the selection line, deafult to 0 (disabled)
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* @param useSTALL activate the stall line, default to false (disabled)
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* @param useLOCK activate the lock line, default to false (disabled)
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* @param useERR activate the error line, default to false (disabled)
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* @param useRTY activate the retry line, default to false (disabled)
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* @param tgaWidth size in bits of the tag address linie, deafult to 0 (disabled)
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* @param tgcWidth size in bits of the tag cycle line, deafult to 0 (disabled)
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* @param tgdWidth size in bits of the tag data line, deafult to 0 (disabled)
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* @param useBTE activate the BTE line, deafult to 0 (disabled)
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* @param useCTI activate the CTI line, deafult to 0 (disabled)
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* @example {{{
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* val wishboneBusConf = new WishboneConfig(32,8).withCycleTag(8).withDataTag(8)
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* val wishboneBus = new Wishbone(wishboneBusConf)
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* }}}
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* @todo test example
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*/
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case class WishboneConfig(
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val addressWidth : Int,
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val dataWidth : Int,
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val selWidth : Int = 0,
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val useSTALL : Boolean = false,
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val useLOCK : Boolean = false,
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val useERR : Boolean = false,
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val useRTY : Boolean = false,
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val tgaWidth : Int = 0,
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val tgcWidth : Int = 0,
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val tgdWidth : Int = 0,
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val useBTE : Boolean = false,
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val useCTI : Boolean = false
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){
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def useTGA = tgaWidth > 0
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def useTGC = tgcWidth > 0
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def useTGD = tgdWidth > 0
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def useSEL = selWidth > 0
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def isPipelined = useSTALL
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def pipelined : WishboneConfig = this.copy(useSTALL = true)
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def withDataTag(size : Int) : WishboneConfig = this.copy(tgdWidth = size)
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def withAddressTag(size : Int) : WishboneConfig = this.copy(tgaWidth = size)
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def withCycleTag(size : Int) : WishboneConfig = this.copy(tgdWidth = size)
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}
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/** This class rappresent a Wishbone bus
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* @param config an istance of WishboneConfig, it will be used to configurate the Wishbone Bus
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*/
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case class Wishbone(config: WishboneConfig) extends Bundle with IMasterSlave {
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/////////////////////
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// MINIMAL SIGNALS //
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/////////////////////
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val CYC = Bool
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val STB = Bool
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||||||
val ACK = Bool
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||||||
val WE = Bool
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||||||
val ADR = UInt(config.addressWidth bits)
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||||||
val DAT_MISO = Bits(config.dataWidth bits)
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||||||
val DAT_MOSI = Bits(config.dataWidth bits)
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||||||
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||||||
///////////////////////////
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|
||||||
// OPTIONAL FLOW CONTROS //
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||||||
///////////////////////////
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|
||||||
val SEL = if(config.useSEL) Bits(config.selWidth bits) else null
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||||||
val STALL = if(config.useSTALL) Bool else null
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||||||
val LOCK = if(config.useLOCK) Bool else null
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||||||
val ERR = if(config.useERR) Bool else null
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||||||
val RTY = if(config.useRTY) Bool else null
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||||||
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||||||
//////////
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||||||
// TAGS //
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||||||
//////////
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val TGD_MISO = if(config.useTGD) Bits(config.tgdWidth bits) else null
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||||||
val TGD_MOSI = if(config.useTGD) Bits(config.tgdWidth bits) else null
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val TGA = if(config.useTGA) Bits(config.tgaWidth bits) else null
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||||||
val TGC = if(config.useTGC) Bits(config.tgcWidth bits) else null
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||||||
val BTE = if(config.useBTE) Bits(2 bits) else null
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||||||
val CTI = if(config.useCTI) Bits(3 bits) else null
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||||||
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||||||
override def asMaster(): Unit = {
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||||||
outWithNull(DAT_MOSI, TGD_MOSI, ADR, CYC, LOCK, SEL, STB, TGA, TGC, WE, CTI, BTE)
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||||||
inWithNull(DAT_MISO, TGD_MISO, ACK, STALL, ERR, RTY)
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|
||||||
}
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||||||
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||||||
// def isCycle : Bool = if(config.useERR) !ERR && CYC else CYC
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||||||
// def isWrite : Bool = isCycle && WE
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||||||
// def isRead : Bool = isCycle && !WE
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|
||||||
// def isReadCycle : Bool = isRead && STB
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|
||||||
// def isWriteCycle : Bool = isWrite && STB
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|
||||||
// def isStalled : Bool = if(config.isPipelined) isCycle && STALL else False
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|
||||||
// def isAcknoledge : Bool = isCycle && ACK
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|
||||||
// def isStrobe : Bool = isCycle && STB
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|
||||||
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|
||||||
// def doSlaveWrite : Bool = this.CYC && this.STB && this.WE
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|
||||||
// def doSlaveRead : Bool = this.CYC && this.STB && !this.WE
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|
||||||
// def doSlavePipelinedWrite : Bool = this.CYC && this.WE
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|
||||||
// def doSlavePipelinedRead : Bool = this.CYC && !this.WE
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|
||||||
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|
||||||
/** Connect the istance of this bus with another, allowing for resize of data
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|
||||||
* @param that the wishbone instance that will be connected and resized
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|
||||||
* @param allowDataResize allow to resize "that" data lines, default to false (disable)
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|
||||||
* @param allowAddressResize allow to resize "that" address lines, default to false (disable)
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|
||||||
* @param allowTagResize allow to resize "that" tag lines, default to false (disable)
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|
||||||
*/
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|
||||||
def connectTo(that : Wishbone, allowDataResize : Boolean = false, allowAddressResize : Boolean = false, allowTagResize : Boolean = false) : Unit = {
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|
||||||
this.CYC <> that.CYC
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|
||||||
this.STB <> that.STB
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|
||||||
this.WE <> that.WE
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|
||||||
this.ACK <> that.ACK
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|
||||||
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|
||||||
if(allowDataResize){
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||||||
this.DAT_MISO.resized <> that.DAT_MISO
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|
||||||
this.DAT_MOSI <> that.DAT_MOSI.resized
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|
||||||
} else {
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|
||||||
this.DAT_MOSI <> that.DAT_MOSI
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|
||||||
this.DAT_MISO <> that.DAT_MISO
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|
||||||
}
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|
||||||
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|
||||||
if(allowAddressResize){
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|
||||||
this.ADR <> that.ADR.resized
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|
||||||
} else {
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|
||||||
this.ADR <> that.ADR
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|
||||||
}
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|
||||||
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|
||||||
///////////////////////////
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|
||||||
// OPTIONAL FLOW CONTROS //
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|
||||||
///////////////////////////
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|
||||||
if(this.config.useSTALL && that.config.useSTALL) this.STALL <> that.STALL
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|
||||||
if(this.config.useERR && that.config.useERR) this.ERR <> that.ERR
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|
||||||
if(this.config.useRTY && that.config.useRTY) this.RTY <> that.RTY
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|
||||||
if(this.config.useSEL && that.config.useSEL) this.SEL <> that.SEL
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|
||||||
if(this.config.useCTI && that.config.useCTI) this.CTI <> that.CTI
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|
||||||
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|
||||||
//////////
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|
||||||
// TAGS //
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|
||||||
//////////
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|
||||||
if(this.config.useTGA && that.config.useTGA)
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|
||||||
if(allowTagResize) this.TGA <> that.TGA.resized else this.TGA <> that.TGA
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|
||||||
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|
||||||
if(this.config.useTGC && that.config.useTGC)
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|
||||||
if(allowTagResize) this.TGC <> that.TGC.resized else this.TGC <> that.TGC
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|
||||||
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|
||||||
if(this.config.useBTE && that.config.useBTE)
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|
||||||
if(allowTagResize) this.BTE <> that.BTE.resized else this.BTE <> that.BTE
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|
||||||
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|
||||||
if(this.config.useTGD && that.config.useTGD){
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|
||||||
if(allowTagResize){
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|
||||||
this.TGD_MISO <> that.TGD_MISO.resized
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|
||||||
this.TGD_MOSI <> that.TGD_MOSI.resized
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|
||||||
} else {
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|
||||||
this.TGD_MISO <> that.TGD_MISO
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|
||||||
this.TGD_MOSI <> that.TGD_MOSI
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|
||||||
}
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|
||||||
}
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|
||||||
}
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|
||||||
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|
||||||
/** Connect common Wishbone signals
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|
||||||
* @example{{{wishbone1 <-> wishbone2}}}
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|
||||||
*/
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|
||||||
def <-> (sink : Wishbone) : Unit = {
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|
||||||
/////////////////////
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|
||||||
// MINIMAL SIGNALS //
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|
||||||
/////////////////////
|
|
||||||
sink.CYC <> this.CYC
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|
||||||
sink.ADR <> this.ADR
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|
||||||
sink.DAT_MOSI <> this.DAT_MOSI
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|
||||||
sink.DAT_MISO <> this.DAT_MISO
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|
||||||
sink.STB <> this.STB
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|
||||||
sink.WE <> this.WE
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|
||||||
sink.ACK <> this.ACK
|
|
||||||
|
|
||||||
///////////////////////////
|
|
||||||
// OPTIONAL FLOW CONTROS //
|
|
||||||
///////////////////////////
|
|
||||||
if(this.config.useSTALL && sink.config.useSTALL) sink.STALL <> this.STALL
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|
||||||
if(this.config.useERR && sink.config.useERR) sink.ERR <> this.ERR
|
|
||||||
if(this.config.useRTY && sink.config.useRTY) sink.RTY <> this.RTY
|
|
||||||
if(this.config.useSEL && sink.config.useSEL) sink.SEL <> this.SEL
|
|
||||||
|
|
||||||
//////////
|
|
||||||
// TAGS //
|
|
||||||
//////////
|
|
||||||
if(this.config.useTGA && sink.config.useTGA) sink.TGA <> this.TGA
|
|
||||||
if(this.config.useTGC && sink.config.useTGC) sink.TGC <> this.TGC
|
|
||||||
if(this.config.useCTI && sink.config.useCTI) sink.CTI <> this.CTI
|
|
||||||
if(this.config.useBTE && sink.config.useBTE) sink.BTE <> this.BTE
|
|
||||||
if(this.config.useTGD && sink.config.useTGD){
|
|
||||||
sink.TGD_MISO <> this.TGD_MISO
|
|
||||||
sink.TGD_MOSI <> this.TGD_MOSI
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/** Clear all the relevant signals in the wishbone bus
|
|
||||||
* @example{{{
|
|
||||||
* val wishbone1 = master(Wishbone(WishboneConfig(8,8)))
|
|
||||||
* val wishbone2 = slave(Wishbone(WishboneConfig(8,8)))
|
|
||||||
* val wishbone2 = slave(Wishbone(WishboneConfig(8,8).withDataTag(8)))
|
|
||||||
*
|
|
||||||
* // this will clear only the following signals: CYC,ADR,DAT_MOSI,STB,WE
|
|
||||||
* wishbone1.clearAll()
|
|
||||||
* // this will clear only the following signals: DAT_MISO,ACK
|
|
||||||
* wishbone2.clearAll()
|
|
||||||
* // this will clear only the following signals: DAT_MISO,ACK,TGD_MISO
|
|
||||||
* wishbone3.clearAll()
|
|
||||||
* }}}
|
|
||||||
*/
|
|
||||||
def clearAll() : Unit = {
|
|
||||||
/////////////////////
|
|
||||||
// MINIMAl SIGLALS //
|
|
||||||
/////////////////////
|
|
||||||
if( isMasterInterface) this.CYC.clear()
|
|
||||||
if( isMasterInterface) this.ADR.clearAll()
|
|
||||||
if( isMasterInterface) this.DAT_MOSI.clearAll()
|
|
||||||
if(!isMasterInterface) this.DAT_MISO.clearAll()
|
|
||||||
if( isMasterInterface) this.STB.clear()
|
|
||||||
if( isMasterInterface) this.WE.clear()
|
|
||||||
if(!isMasterInterface) this.ACK.clear()
|
|
||||||
|
|
||||||
///////////////////////////
|
|
||||||
// OPTIONAL FLOW CONTROS //
|
|
||||||
///////////////////////////
|
|
||||||
if(this.config.useSTALL && !isMasterInterface) this.STALL.clear()
|
|
||||||
if(this.config.useERR && !isMasterInterface) this.ERR.clear()
|
|
||||||
if(this.config.useRTY && !isMasterInterface) this.RTY.clear()
|
|
||||||
if(this.config.useSEL && isMasterInterface) this.SEL.clearAll()
|
|
||||||
|
|
||||||
//////////
|
|
||||||
// TAGS //
|
|
||||||
//////////
|
|
||||||
if(this.config.useTGA && isMasterInterface) this.TGA.clearAll()
|
|
||||||
if(this.config.useTGC && isMasterInterface) this.TGC.clearAll()
|
|
||||||
if(this.config.useCTI && isMasterInterface) this.CTI.clearAll()
|
|
||||||
if(this.config.useBTE && isMasterInterface) this.BTE.clearAll()
|
|
||||||
if(this.config.useTGD && !isMasterInterface) this.TGD_MISO.clearAll()
|
|
||||||
if(this.config.useTGD && isMasterInterface) this.TGD_MOSI.clearAll()
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
@ -4,7 +4,7 @@ package vexriscv.demo
|
||||||
import spinal.core._
|
import spinal.core._
|
||||||
import spinal.lib._
|
import spinal.lib._
|
||||||
import spinal.lib.bus.avalon.AvalonMM
|
import spinal.lib.bus.avalon.AvalonMM
|
||||||
import spinal.lib.com.jtag.Jtag
|
import spinal.lib.com.jtag.{Jtag, JtagTapInstructionCtrl}
|
||||||
import spinal.lib.eda.altera.{InterruptReceiverTag, QSysify, ResetEmitterTag}
|
import spinal.lib.eda.altera.{InterruptReceiverTag, QSysify, ResetEmitterTag}
|
||||||
import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig}
|
import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig}
|
||||||
import vexriscv.plugin._
|
import vexriscv.plugin._
|
||||||
|
|
@ -163,6 +163,11 @@ object VexRiscvAhbLite3{
|
||||||
plugin.io.bus.setAsDirectionLess()
|
plugin.io.bus.setAsDirectionLess()
|
||||||
val jtag = slave(new Jtag()).setName("jtag")
|
val jtag = slave(new Jtag()).setName("jtag")
|
||||||
jtag <> plugin.io.bus.fromJtag()
|
jtag <> plugin.io.bus.fromJtag()
|
||||||
|
|
||||||
|
// // On Artix FPGA jtag :
|
||||||
|
// val jtagCtrl = JtagTapInstructionCtrl()
|
||||||
|
// val tap = jtagCtrl.fromXilinxBscane2(userId = 1)
|
||||||
|
// jtagCtrl <> plugin.io.bus.fromJtagInstructionCtrl(ClockDomain(tap.TCK))
|
||||||
}
|
}
|
||||||
case _ =>
|
case _ =>
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -1,7 +1,7 @@
|
||||||
package vexriscv.plugin
|
package vexriscv.plugin
|
||||||
|
|
||||||
import spinal.lib.com.jtag.Jtag
|
import spinal.lib.com.jtag.{Jtag, JtagTapInstructionCtrl}
|
||||||
import spinal.lib.system.debugger.{JtagBridge, SystemDebugger, SystemDebuggerConfig}
|
import spinal.lib.system.debugger.{JtagBridge, JtagBridgeNoTap, SystemDebugger, SystemDebuggerConfig, SystemDebuggerMemBus}
|
||||||
import vexriscv.plugin.IntAluPlugin.{ALU_CTRL, AluCtrlEnum}
|
import vexriscv.plugin.IntAluPlugin.{ALU_CTRL, AluCtrlEnum}
|
||||||
import vexriscv._
|
import vexriscv._
|
||||||
import vexriscv.ip._
|
import vexriscv.ip._
|
||||||
|
|
@ -63,6 +63,18 @@ case class DebugExtensionBus() extends Bundle with IMasterSlave{
|
||||||
bus
|
bus
|
||||||
}
|
}
|
||||||
|
|
||||||
|
def from(c : SystemDebuggerConfig) : SystemDebuggerMemBus = {
|
||||||
|
val mem = SystemDebuggerMemBus(c)
|
||||||
|
cmd.valid := mem.cmd.valid
|
||||||
|
cmd.wr := mem.cmd.wr
|
||||||
|
cmd.data := mem.cmd.data
|
||||||
|
cmd.address := mem.cmd.address.resized
|
||||||
|
mem.cmd.ready := cmd.ready
|
||||||
|
mem.rsp.valid := RegNext(cmd.fire).init(False)
|
||||||
|
mem.rsp.payload := rsp.data
|
||||||
|
mem
|
||||||
|
}
|
||||||
|
|
||||||
def fromJtag(): Jtag ={
|
def fromJtag(): Jtag ={
|
||||||
val jtagConfig = SystemDebuggerConfig(
|
val jtagConfig = SystemDebuggerConfig(
|
||||||
memAddressWidth = 32,
|
memAddressWidth = 32,
|
||||||
|
|
@ -72,16 +84,24 @@ case class DebugExtensionBus() extends Bundle with IMasterSlave{
|
||||||
val jtagBridge = new JtagBridge(jtagConfig)
|
val jtagBridge = new JtagBridge(jtagConfig)
|
||||||
val debugger = new SystemDebugger(jtagConfig)
|
val debugger = new SystemDebugger(jtagConfig)
|
||||||
debugger.io.remote <> jtagBridge.io.remote
|
debugger.io.remote <> jtagBridge.io.remote
|
||||||
debugger.io.mem.cmd.valid <> cmd.valid
|
debugger.io.mem <> this.from(jtagConfig)
|
||||||
debugger.io.mem.cmd.ready <> cmd.ready
|
|
||||||
debugger.io.mem.cmd.wr <> cmd.wr
|
|
||||||
cmd.address := debugger.io.mem.cmd.address.resized
|
|
||||||
debugger.io.mem.cmd.data <> cmd.data
|
|
||||||
debugger.io.mem.rsp.valid <> RegNext(cmd.fire).init(False)
|
|
||||||
debugger.io.mem.rsp.payload <> rsp.data
|
|
||||||
|
|
||||||
jtagBridge.io.jtag
|
jtagBridge.io.jtag
|
||||||
}
|
}
|
||||||
|
|
||||||
|
def fromJtagInstructionCtrl(jtagClockDomain : ClockDomain): JtagTapInstructionCtrl ={
|
||||||
|
val jtagConfig = SystemDebuggerConfig(
|
||||||
|
memAddressWidth = 32,
|
||||||
|
memDataWidth = 32,
|
||||||
|
remoteCmdWidth = 1
|
||||||
|
)
|
||||||
|
val jtagBridge = new JtagBridgeNoTap(jtagConfig, jtagClockDomain)
|
||||||
|
val debugger = new SystemDebugger(jtagConfig)
|
||||||
|
debugger.io.remote <> jtagBridge.io.remote
|
||||||
|
debugger.io.mem <> this.from(jtagConfig)
|
||||||
|
|
||||||
|
jtagBridge.io.ctrl
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
case class DebugExtensionIo() extends Bundle with IMasterSlave{
|
case class DebugExtensionIo() extends Bundle with IMasterSlave{
|
||||||
|
|
|
||||||
|
|
@ -401,7 +401,7 @@ public:
|
||||||
sdramIo->ADDR = &top->io_sdram_ADDR ;
|
sdramIo->ADDR = &top->io_sdram_ADDR ;
|
||||||
sdramIo->DQ_read = (CData*)&top->io_sdram_DQ_read ;
|
sdramIo->DQ_read = (CData*)&top->io_sdram_DQ_read ;
|
||||||
sdramIo->DQ_write = (CData*)&top->io_sdram_DQ_write ;
|
sdramIo->DQ_write = (CData*)&top->io_sdram_DQ_write ;
|
||||||
sdramIo->DQ_writeEnable = &top->io_sdram_DQ_writeEnable;
|
sdramIo->DQ_writeEnable = (CData*)&top->io_sdram_DQ_writeEnable;
|
||||||
Sdram *sdram = new Sdram(sdramConfig, sdramIo);
|
Sdram *sdram = new Sdram(sdramConfig, sdramIo);
|
||||||
|
|
||||||
axiClk->add(sdram);
|
axiClk->add(sdram);
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue