Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Moved KeepAttribute to spinal.lib

This commit is contained in:
Charles Papon 2019-12-24 00:43:36 +01:00
parent 052c8dd602
commit 3b494e97cd
2 changed files with 1 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/vexriscv/ip/InstructionCache.scala
View File

@ -8,7 +8,7 @@ import spinal.lib.bus.avalon.{AvalonMM, AvalonMMConfig}
import spinal.lib.bus.bmb.{Bmb, BmbParameter} import spinal.lib.bus.bmb.{Bmb, BmbParameter}
import spinal.lib.bus.wishbone.{Wishbone, WishboneConfig} import spinal.lib.bus.wishbone.{Wishbone, WishboneConfig}
import spinal.lib.bus.simple._ import spinal.lib.bus.simple._
import vexriscv.plugin.{IBusSimpleBus, IBusSimplePlugin, KeepAttribute} import vexriscv.plugin.{IBusSimpleBus, IBusSimplePlugin}
case class InstructionCacheConfig( cacheSize : Int, case class InstructionCacheConfig( cacheSize : Int,

13
src/main/scala/vexriscv/plugin/PcManagerSimplePlugin.scala
View File

@ -8,19 +8,6 @@ import scala.collection.mutable.ArrayBuffer
object KeepAttribute{
object syn_keep_verilog extends AttributeFlag("synthesis syn_keep = 1", COMMENT_ATTRIBUTE){
override def isLanguageReady(language: Language) : Boolean = language == Language.VERILOG || language == Language.SYSTEM_VERILOG
}
object syn_keep_vhdl extends AttributeFlag("syn_keep"){
override def isLanguageReady(language: Language) : Boolean = language == Language.VHDL
}
object keep extends AttributeFlag("keep")
def apply[T <: Data](that : T) = that.addAttribute(keep).addAttribute(syn_keep_verilog).addAttribute(syn_keep_vhdl)
}
class PcManagerSimplePlugin(resetVector : BigInt, class PcManagerSimplePlugin(resetVector : BigInt,
relaxedPcCalculation : Boolean = false, relaxedPcCalculation : Boolean = false,