Moved KeepAttribute to spinal.lib
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@ -8,7 +8,7 @@ import spinal.lib.bus.avalon.{AvalonMM, AvalonMMConfig}
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import spinal.lib.bus.bmb.{Bmb, BmbParameter}
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import spinal.lib.bus.wishbone.{Wishbone, WishboneConfig}
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import spinal.lib.bus.simple._
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import vexriscv.plugin.{IBusSimpleBus, IBusSimplePlugin, KeepAttribute}
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import vexriscv.plugin.{IBusSimpleBus, IBusSimplePlugin}
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case class InstructionCacheConfig( cacheSize : Int,
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@ -8,19 +8,6 @@ import scala.collection.mutable.ArrayBuffer
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object KeepAttribute{
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object syn_keep_verilog extends AttributeFlag("synthesis syn_keep = 1", COMMENT_ATTRIBUTE){
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override def isLanguageReady(language: Language) : Boolean = language == Language.VERILOG || language == Language.SYSTEM_VERILOG
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}
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object syn_keep_vhdl extends AttributeFlag("syn_keep"){
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override def isLanguageReady(language: Language) : Boolean = language == Language.VHDL
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}
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object keep extends AttributeFlag("keep")
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def apply[T <: Data](that : T) = that.addAttribute(keep).addAttribute(syn_keep_verilog).addAttribute(syn_keep_vhdl)
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}
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class PcManagerSimplePlugin(resetVector : BigInt,
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relaxedPcCalculation : Boolean = false,
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