Remove usages of implicit string to B/U/S
This commit is contained in:
parent
f1959ff830
commit
3d34d754a9
|
@ -259,7 +259,7 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
|
|||
val cmdBridge = Stream (DataCacheMemCmd(p))
|
||||
val isBurst = cmdBridge.length =/= 0
|
||||
cmdBridge.valid := cmd.valid
|
||||
cmdBridge.address := (isBurst ? (cmd.address(31 downto widthOf(counter) + 2) @@ counter @@ "00") | (cmd.address(31 downto 2) @@ "00"))
|
||||
cmdBridge.address := (isBurst ? (cmd.address(31 downto widthOf(counter) + 2) @@ counter @@ U"00") | (cmd.address(31 downto 2) @@ U"00"))
|
||||
cmdBridge.wr := cmd.wr
|
||||
cmdBridge.mask := cmd.mask
|
||||
cmdBridge.data := cmd.data
|
||||
|
@ -278,8 +278,8 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
|
|||
|
||||
bus.ADR := cmdBridge.address >> 2
|
||||
bus.CTI := Mux(isBurst, cmdBridge.last ? B"111" | B"010", B"000")
|
||||
bus.BTE := "00"
|
||||
bus.SEL := cmdBridge.wr ? cmdBridge.mask | "1111"
|
||||
bus.BTE := B"00"
|
||||
bus.SEL := cmdBridge.wr ? cmdBridge.mask | B"1111"
|
||||
bus.WE := cmdBridge.wr
|
||||
bus.DAT_MOSI := cmdBridge.data
|
||||
|
||||
|
|
|
@ -197,7 +197,7 @@ class BranchPlugin(earlyBranch : Boolean,
|
|||
).asUInt
|
||||
|
||||
val branchAdder = branch_src1 + branch_src2
|
||||
insert(BRANCH_CALC) := branchAdder(31 downto 1) @@ "0"
|
||||
insert(BRANCH_CALC) := branchAdder(31 downto 1) @@ U"0"
|
||||
}
|
||||
|
||||
//Apply branchs (JAL,JALR, Bxx)
|
||||
|
@ -274,7 +274,7 @@ class BranchPlugin(earlyBranch : Boolean,
|
|||
}
|
||||
}
|
||||
val branchAdder = branch_src1 + branch_src2
|
||||
insert(BRANCH_CALC) := branchAdder(31 downto 1) @@ "0"
|
||||
insert(BRANCH_CALC) := branchAdder(31 downto 1) @@ U"0"
|
||||
}
|
||||
|
||||
|
||||
|
@ -341,7 +341,7 @@ class BranchPlugin(earlyBranch : Boolean,
|
|||
).asUInt
|
||||
|
||||
val branchAdder = branch_src1 + input(BRANCH_SRC2)
|
||||
insert(BRANCH_CALC) := branchAdder(31 downto 1) @@ "0"
|
||||
insert(BRANCH_CALC) := branchAdder(31 downto 1) @@ U"0"
|
||||
insert(NEXT_PC) := input(PC) + (if(pipeline(RVC_GEN)) ((input(IS_RVC)) ? U(2) | U(4)) else 4)
|
||||
insert(TARGET_MISSMATCH) := decode.input(PC) =/= input(BRANCH_CALC)
|
||||
}
|
||||
|
|
|
@ -775,8 +775,8 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
|
|||
var privilegs = if (supervisorGen) List(1, 3) else List(3)
|
||||
val targetPrivilege = if(pipelinedInterrupt) Reg(UInt(2 bits)) else UInt(2 bits).assignDontCare()
|
||||
val privilegeAllowInterrupts = mutable.HashMap[Int, Bool]()
|
||||
if (supervisorGen) privilegeAllowInterrupts += 1 -> ((sstatus.SIE && privilege === "01") || privilege < "01")
|
||||
privilegeAllowInterrupts += 3 -> (mstatus.MIE || privilege < "11")
|
||||
if (supervisorGen) privilegeAllowInterrupts += 1 -> ((sstatus.SIE && privilege === U"01") || privilege < U"01")
|
||||
privilegeAllowInterrupts += 3 -> (mstatus.MIE || privilege < U"11")
|
||||
while (privilegs.nonEmpty) {
|
||||
val p = privilegs.head
|
||||
when(privilegeAllowInterrupts(p)) {
|
||||
|
@ -844,7 +844,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
|
|||
fetcher.haltIt() //Avoid having the fetch confused by the incomming privilege switch
|
||||
|
||||
jumpInterface.valid := True
|
||||
jumpInterface.payload := (if(!xtvecModeGen) xtvec.base @@ "00" else (xtvec.mode === 0 || hadException) ? (xtvec.base @@ "00") | ((xtvec.base + trapCause) @@ "00") )
|
||||
jumpInterface.payload := (if(!xtvecModeGen) xtvec.base @@ U"00" else (xtvec.mode === 0 || hadException) ? (xtvec.base @@ U"00") | ((xtvec.base + trapCause) @@ U"00") )
|
||||
lastStage.arbitration.flushNext := True
|
||||
|
||||
if(privilegeGen) privilegeReg := targetPrivilege
|
||||
|
@ -917,8 +917,8 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
|
|||
|
||||
val imm = IMM(input(INSTRUCTION))
|
||||
insert(CSR_WRITE_OPCODE) := ! (
|
||||
(input(INSTRUCTION)(14 downto 13) === "01" && input(INSTRUCTION)(rs1Range) === 0)
|
||||
|| (input(INSTRUCTION)(14 downto 13) === "11" && imm.z === 0)
|
||||
(input(INSTRUCTION)(14 downto 13) === B"01" && input(INSTRUCTION)(rs1Range) === 0)
|
||||
|| (input(INSTRUCTION)(14 downto 13) === B"11" && imm.z === 0)
|
||||
)
|
||||
insert(CSR_READ_OPCODE) := input(INSTRUCTION)(13 downto 7) =/= B"0100000"
|
||||
}
|
||||
|
|
|
@ -211,7 +211,7 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
|
|||
if (catchSomething) {
|
||||
decodeExceptionPort.valid := False
|
||||
decodeExceptionPort.code.assignDontCare()
|
||||
decodeExceptionPort.badAddr := cacheRsp.pc(31 downto 2) @@ "00"
|
||||
decodeExceptionPort.badAddr := cacheRsp.pc(31 downto 2) @@ U"00"
|
||||
}
|
||||
|
||||
when(cacheRsp.isValid && cacheRsp.mmuRefilling && !issueDetected) {
|
||||
|
|
|
@ -316,7 +316,7 @@ class IBusSimplePlugin( resetVector : BigInt,
|
|||
mmuBus.cmd.bypassTranslation := False
|
||||
mmuBus.end := cmdForkStage.output.fire || fetcherflushIt
|
||||
|
||||
cmd.pc := mmuBus.rsp.physicalAddress(31 downto 2) @@ "00"
|
||||
cmd.pc := mmuBus.rsp.physicalAddress(31 downto 2) @@ U"00"
|
||||
|
||||
//do not emit memory request if MMU miss
|
||||
when(mmuBus.rsp.exception || mmuBus.rsp.refilling){
|
||||
|
@ -333,7 +333,7 @@ class IBusSimplePlugin( resetVector : BigInt,
|
|||
}
|
||||
|
||||
val mmuLess = (mmuBus == null) generate new Area{
|
||||
cmd.pc := cmdForkStage.input.payload(31 downto 2) @@ "00"
|
||||
cmd.pc := cmdForkStage.input.payload(31 downto 2) @@ U"00"
|
||||
}
|
||||
|
||||
val rspJoin = new Area {
|
||||
|
@ -389,7 +389,7 @@ class IBusSimplePlugin( resetVector : BigInt,
|
|||
|
||||
if(catchSomething){
|
||||
decodeExceptionPort.code.assignDontCare()
|
||||
decodeExceptionPort.badAddr := join.pc(31 downto 2) @@ "00"
|
||||
decodeExceptionPort.badAddr := join.pc(31 downto 2) @@ U"00"
|
||||
|
||||
if(catchAccessFault) when(join.valid && join.rsp.error){
|
||||
decodeExceptionPort.code := 1
|
||||
|
|
|
@ -50,7 +50,7 @@ object RvcDecompressor{
|
|||
ret := (i(11 downto 7) === 2) ? addi16sp | lui
|
||||
}
|
||||
is(12){
|
||||
val isImmediate = i(11 downto 10) =/= "11"
|
||||
val isImmediate = i(11 downto 10) =/= B"11"
|
||||
val isShift = !i(11)
|
||||
val func3 = i(11 downto 10).mux(
|
||||
0 -> B"101",
|
||||
|
@ -64,7 +64,7 @@ object RvcDecompressor{
|
|||
)
|
||||
)
|
||||
val msbs = Mux(
|
||||
sel = i(11 downto 10) === "10",
|
||||
sel = i(11 downto 10) === B"10",
|
||||
whenTrue = B((6 downto 0) -> i(12)), //andi
|
||||
whenFalse = B"0" ## (i(11 downto 10) === B"01" || (i(11 downto 10) === B"11" && i(6 downto 5) === B"00")) ## B"00000"
|
||||
)
|
||||
|
|
|
@ -167,7 +167,7 @@ class MulDivIterativePlugin(genMul : Boolean = true,
|
|||
}
|
||||
|
||||
if(dhrystoneOpt) {
|
||||
execute.insert(FAST_DIV_VALID) := execute.input(IS_DIV) && execute.input(INSTRUCTION)(13 downto 12) === "00" && !execute.input(RS1).msb && !execute.input(RS2).msb && execute.input(RS1).asUInt < 16 && execute.input(RS2).asUInt < 16 && execute.input(RS2) =/= 0
|
||||
execute.insert(FAST_DIV_VALID) := execute.input(IS_DIV) && execute.input(INSTRUCTION)(13 downto 12) === B"00" && !execute.input(RS1).msb && !execute.input(RS2).msb && execute.input(RS1).asUInt < 16 && execute.input(RS2).asUInt < 16 && execute.input(RS2) =/= 0
|
||||
execute.insert(FAST_DIV_VALUE) := (0 to 15).flatMap(n => (0 to 15).map(d => U(if (d == 0) 0 else n / d, 4 bits))).read(U(execute.input(RS1)(3 downto 0)) @@ U(execute.input(RS2)(3 downto 0))) //(U(execute.input(RS1)(3 downto 0)) / U(execute.input(RS2)(3 downto 0))
|
||||
when(execute.input(FAST_DIV_VALID)) {
|
||||
execute.output(IS_DIV) := False
|
||||
|
|
Loading…
Reference in New Issue