Add optional XIP to Murax

This commit is contained in:
Dolu1990 2018-09-16 11:00:56 +02:00
parent 312e8b99b8
commit 3e17461cc7
3 changed files with 89 additions and 29 deletions

View File

@ -1,20 +1,42 @@
name := "VexRiscv" //name := "VexRiscv"
//
//organization := "com.github.spinalhdl"
//
//version := "1.0.0"
//
//scalaVersion := "2.11.6"
//
//EclipseKeys.withSource := true
//
//libraryDependencies ++= Seq(
// "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.2.1",
// "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.2.1",
// "org.scalatest" % "scalatest_2.11" % "2.2.1",
// "org.yaml" % "snakeyaml" % "1.8"
//)
//
//
//
//addCompilerPlugin("org.scala-lang.plugins" % "scala-continuations-plugin_2.11.6" % "1.0.2")
//scalacOptions += "-P:continuations:enable"
//fork := true
organization := "com.github.spinalhdl" lazy val root = (project in file(".")).
settings(
version := "1.0.0" inThisBuild(List(
organization := "com.github.spinalhdl",
scalaVersion := "2.11.6" scalaVersion := "2.11.6",
version := "1.0.0"
EclipseKeys.withSource := true )),
libraryDependencies ++= Seq(
libraryDependencies ++= Seq(
"com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.2.0",
"com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.2.0",
"org.scalatest" % "scalatest_2.11" % "2.2.1", "org.scalatest" % "scalatest_2.11" % "2.2.1",
"org.yaml" % "snakeyaml" % "1.8" "org.yaml" % "snakeyaml" % "1.8"
) ),
name := "VexRiscv"
).dependsOn(spinalHdlSim,spinalHdlCore,spinalHdlLib)
lazy val spinalHdlSim = ProjectRef(file("../SpinalHDL"), "SpinalHDL-sim")
lazy val spinalHdlCore = ProjectRef(file("../SpinalHDL"), "SpinalHDL-core")
lazy val spinalHdlLib = ProjectRef(file("../SpinalHDL"), "SpinalHDL-lib")
addCompilerPlugin("org.scala-lang.plugins" % "scala-continuations-plugin_2.11.6" % "1.0.2") addCompilerPlugin("org.scala-lang.plugins" % "scala-continuations-plugin_2.11.6" % "1.0.2")

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@ -5,13 +5,14 @@ import spinal.lib._
import spinal.lib.bus.amba3.apb._ import spinal.lib.bus.amba3.apb._
import spinal.lib.bus.misc.SizeMapping import spinal.lib.bus.misc.SizeMapping
import spinal.lib.com.jtag.Jtag import spinal.lib.com.jtag.Jtag
import spinal.lib.com.spi.ddr.SpiDdrMaster
import spinal.lib.com.uart._ import spinal.lib.com.uart._
import spinal.lib.io.{InOutWrapper, TriStateArray} import spinal.lib.io.{InOutWrapper, TriStateArray}
import spinal.lib.misc.{InterruptCtrl, Prescaler, Timer} import spinal.lib.misc.{InterruptCtrl, Prescaler, Timer}
import spinal.lib.soc.pinsec.{PinsecTimerCtrl, PinsecTimerCtrlExternal} import spinal.lib.soc.pinsec.{PinsecTimerCtrl, PinsecTimerCtrlExternal}
import vexriscv.plugin._ import vexriscv.plugin._
import vexriscv.{VexRiscv, VexRiscvConfig, plugin} import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
import spinal.lib.com.spi.ddr._
import scala.collection.mutable.ArrayBuffer import scala.collection.mutable.ArrayBuffer
/** /**
@ -38,10 +39,21 @@ case class MuraxConfig(coreFrequency : HertzNumber,
pipelineApbBridge : Boolean, pipelineApbBridge : Boolean,
gpioWidth : Int, gpioWidth : Int,
uartCtrlConfig : UartCtrlMemoryMappedConfig, uartCtrlConfig : UartCtrlMemoryMappedConfig,
xipConfig : SpiDdrMasterCtrl.MemoryMappingParameters,
cpuPlugins : ArrayBuffer[Plugin[VexRiscv]]){ cpuPlugins : ArrayBuffer[Plugin[VexRiscv]]){
require(pipelineApbBridge || pipelineMainBus, "At least pipelineMainBus or pipelineApbBridge should be enable to avoid wipe transactions") require(pipelineApbBridge || pipelineMainBus, "At least pipelineMainBus or pipelineApbBridge should be enable to avoid wipe transactions")
val genXpi = xipConfig != null
def addXip(): MuraxConfig = copy(xipConfig = SpiDdrMasterCtrl.MemoryMappingParameters(
SpiDdrMasterCtrl.Parameters(8, 12, SpiDdrParameter(4, 1)).addAllMods(),
cmdFifoDepth = 32,
rspFifoDepth = 32,
xip = SpiDdrMasterCtrl.XipBusParameters(addressWidth = 24, dataWidth = 32)
))
} }
object MuraxConfig{ object MuraxConfig{
def default = MuraxConfig( def default = MuraxConfig(
coreFrequency = 12 MHz, coreFrequency = 12 MHz,
@ -51,6 +63,7 @@ object MuraxConfig{
pipelineMainBus = false, pipelineMainBus = false,
pipelineApbBridge = true, pipelineApbBridge = true,
gpioWidth = 32, gpioWidth = 32,
xipConfig = null,
cpuPlugins = ArrayBuffer( //DebugPlugin added by the toplevel cpuPlugins = ArrayBuffer( //DebugPlugin added by the toplevel
new IBusSimplePlugin( new IBusSimplePlugin(
resetVector = 0x80000000l, resetVector = 0x80000000l,
@ -146,6 +159,8 @@ case class Murax(config : MuraxConfig) extends Component{
//Peripherals IO //Peripherals IO
val gpioA = master(TriStateArray(gpioWidth bits)) val gpioA = master(TriStateArray(gpioWidth bits))
val uart = master(Uart()) val uart = master(Uart())
val xpi = ifGen(genXpi)(master(SpiDdrMaster(xipConfig.ctrl.spi)))
} }
@ -232,11 +247,13 @@ case class Murax(config : MuraxConfig) extends Component{
//****** MainBus slaves ******** //****** MainBus slaves ********
val mainBusMapping = ArrayBuffer[(SimpleBus,SizeMapping)]()
val ram = new MuraxSimpleBusRam( val ram = new MuraxSimpleBusRam(
onChipRamSize = onChipRamSize, onChipRamSize = onChipRamSize,
onChipRamHexFile = onChipRamHexFile, onChipRamHexFile = onChipRamHexFile,
simpleBusConfig = simpleBusConfig simpleBusConfig = simpleBusConfig
) )
mainBusMapping += ram.io.bus -> (0x80000000l, onChipRamSize)
val apbBridge = new MuraxSimpleBusToApbBridge( val apbBridge = new MuraxSimpleBusToApbBridge(
apb3Config = Apb3Config( apb3Config = Apb3Config(
@ -246,39 +263,54 @@ case class Murax(config : MuraxConfig) extends Component{
pipelineBridge = pipelineApbBridge, pipelineBridge = pipelineApbBridge,
simpleBusConfig = simpleBusConfig simpleBusConfig = simpleBusConfig
) )
mainBusMapping += apbBridge.io.simpleBus -> (0xF0000000l, 1 MB)
//******** APB peripherals ********* //******** APB peripherals *********
val apbMapping = ArrayBuffer[(Apb3, SizeMapping)]()
val gpioACtrl = Apb3Gpio(gpioWidth = gpioWidth) val gpioACtrl = Apb3Gpio(gpioWidth = gpioWidth)
io.gpioA <> gpioACtrl.io.gpio io.gpioA <> gpioACtrl.io.gpio
apbMapping += gpioACtrl.io.apb -> (0x00000, 4 kB)
val uartCtrl = Apb3UartCtrl(uartCtrlConfig) val uartCtrl = Apb3UartCtrl(uartCtrlConfig)
uartCtrl.io.uart <> io.uart uartCtrl.io.uart <> io.uart
externalInterrupt setWhen(uartCtrl.io.interrupt) externalInterrupt setWhen(uartCtrl.io.interrupt)
apbMapping += uartCtrl.io.apb -> (0x10000, 4 kB)
val timer = new MuraxApb3Timer() val timer = new MuraxApb3Timer()
timerInterrupt setWhen(timer.io.interrupt) timerInterrupt setWhen(timer.io.interrupt)
apbMapping += timer.io.apb -> (0x20000, 4 kB)
val xpi = ifGen(genXpi)(new Area{
val ctrl = Apb3SpiDdrMasterCtrl(xipConfig)
ctrl.io.spi <> io.xpi
externalInterrupt setWhen(ctrl.io.interrupt)
apbMapping += ctrl.io.apb -> (0x1F000, 4 kB)
val accessBus = new SimpleBus(SimpleBusConfig(24,32))
mainBusMapping += accessBus -> (0x90000000l, 16 MB)
ctrl.io.xip.cmd.valid <> (accessBus.cmd.valid && !accessBus.cmd.wr)
ctrl.io.xip.cmd.ready <> accessBus.cmd.ready
ctrl.io.xip.cmd.payload <> accessBus.cmd.address
ctrl.io.xip.rsp.valid <> accessBus.rsp.valid
ctrl.io.xip.rsp.payload <> accessBus.rsp.data
})
//******** Memory mappings ********* //******** Memory mappings *********
val apbDecoder = Apb3Decoder( val apbDecoder = Apb3Decoder(
master = apbBridge.io.apb, master = apbBridge.io.apb,
slaves = List[(Apb3, SizeMapping)]( slaves = apbMapping
gpioACtrl.io.apb -> (0x00000, 4 kB),
uartCtrl.io.apb -> (0x10000, 4 kB),
timer.io.apb -> (0x20000, 4 kB)
)
) )
val mainBusDecoder = new Area { val mainBusDecoder = new Area {
val logic = new MuraxSimpleBusDecoder( val logic = new MuraxSimpleBusDecoder(
master = mainBusArbiter.io.masterBus, master = mainBusArbiter.io.masterBus,
specification = List[(SimpleBus,SizeMapping)]( specification = mainBusMapping,
ram.io.bus -> (0x80000000l, onChipRamSize),
apbBridge.io.simpleBus -> (0xF0000000l, 1 MB)
),
pipelineMaster = pipelineMainBus pipelineMaster = pipelineMainBus
) )
} }
@ -293,6 +325,12 @@ object Murax{
} }
} }
object MuraxWithXip{
def main(args: Array[String]) {
SpinalVerilog(Murax(MuraxConfig.default.addXip()))
}
}
object MuraxDhrystoneReady{ object MuraxDhrystoneReady{
def main(args: Array[String]) { def main(args: Array[String]) {
SpinalVerilog(Murax(MuraxConfig.fast.copy(onChipRamSize = 256 kB))) SpinalVerilog(Murax(MuraxConfig.fast.copy(onChipRamSize = 256 kB)))

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@ -130,7 +130,7 @@ class MuraxSimpleBusToApbBridge(apb3Config: Apb3Config, pipelineBridge : Boolean
} }
} }
class MuraxSimpleBusDecoder(master : SimpleBus, val specification : List[(SimpleBus,SizeMapping)], pipelineMaster : Boolean) extends Area{ class MuraxSimpleBusDecoder(master : SimpleBus, val specification : Seq[(SimpleBus,SizeMapping)], pipelineMaster : Boolean) extends Area{
val masterPipelined = SimpleBus(master.config) val masterPipelined = SimpleBus(master.config)
if(!pipelineMaster) { if(!pipelineMaster) {
masterPipelined.cmd << master.cmd masterPipelined.cmd << master.cmd
@ -146,7 +146,7 @@ class MuraxSimpleBusDecoder(master : SimpleBus, val specification : List[(Simple
val hits = for((slaveBus, memorySpace) <- specification) yield { val hits = for((slaveBus, memorySpace) <- specification) yield {
val hit = memorySpace.hit(masterPipelined.cmd.address) val hit = memorySpace.hit(masterPipelined.cmd.address)
slaveBus.cmd.valid := masterPipelined.cmd.valid && hit slaveBus.cmd.valid := masterPipelined.cmd.valid && hit
slaveBus.cmd.payload := masterPipelined.cmd.payload slaveBus.cmd.payload := masterPipelined.cmd.payload.resized
hit hit
} }
val noHit = !hits.orR val noHit = !hits.orR