Add optional XIP to Murax
This commit is contained in:
parent
312e8b99b8
commit
3e17461cc7
56
build.sbt
56
build.sbt
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@ -1,22 +1,44 @@
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name := "VexRiscv"
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//name := "VexRiscv"
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//
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organization := "com.github.spinalhdl"
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//organization := "com.github.spinalhdl"
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//
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version := "1.0.0"
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//version := "1.0.0"
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//
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scalaVersion := "2.11.6"
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//scalaVersion := "2.11.6"
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//
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EclipseKeys.withSource := true
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//EclipseKeys.withSource := true
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//
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libraryDependencies ++= Seq(
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//libraryDependencies ++= Seq(
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"com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.2.0",
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// "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.2.1",
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"com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.2.0",
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// "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.2.1",
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"org.scalatest" % "scalatest_2.11" % "2.2.1",
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// "org.scalatest" % "scalatest_2.11" % "2.2.1",
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"org.yaml" % "snakeyaml" % "1.8"
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// "org.yaml" % "snakeyaml" % "1.8"
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)
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//)
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//
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//
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//
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//addCompilerPlugin("org.scala-lang.plugins" % "scala-continuations-plugin_2.11.6" % "1.0.2")
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//scalacOptions += "-P:continuations:enable"
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//fork := true
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lazy val root = (project in file(".")).
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settings(
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inThisBuild(List(
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organization := "com.github.spinalhdl",
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scalaVersion := "2.11.6",
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version := "1.0.0"
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)),
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libraryDependencies ++= Seq(
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"org.scalatest" % "scalatest_2.11" % "2.2.1",
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"org.yaml" % "snakeyaml" % "1.8"
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),
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name := "VexRiscv"
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).dependsOn(spinalHdlSim,spinalHdlCore,spinalHdlLib)
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lazy val spinalHdlSim = ProjectRef(file("../SpinalHDL"), "SpinalHDL-sim")
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lazy val spinalHdlCore = ProjectRef(file("../SpinalHDL"), "SpinalHDL-core")
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lazy val spinalHdlLib = ProjectRef(file("../SpinalHDL"), "SpinalHDL-lib")
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addCompilerPlugin("org.scala-lang.plugins" % "scala-continuations-plugin_2.11.6" % "1.0.2")
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addCompilerPlugin("org.scala-lang.plugins" % "scala-continuations-plugin_2.11.6" % "1.0.2")
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scalacOptions += "-P:continuations:enable"
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scalacOptions += "-P:continuations:enable"
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fork := true
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fork := true
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@ -5,13 +5,14 @@ import spinal.lib._
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import spinal.lib.bus.amba3.apb._
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import spinal.lib.bus.amba3.apb._
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import spinal.lib.bus.misc.SizeMapping
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import spinal.lib.bus.misc.SizeMapping
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import spinal.lib.com.jtag.Jtag
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import spinal.lib.com.jtag.Jtag
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import spinal.lib.com.spi.ddr.SpiDdrMaster
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import spinal.lib.com.uart._
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import spinal.lib.com.uart._
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import spinal.lib.io.{InOutWrapper, TriStateArray}
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import spinal.lib.io.{InOutWrapper, TriStateArray}
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import spinal.lib.misc.{InterruptCtrl, Prescaler, Timer}
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import spinal.lib.misc.{InterruptCtrl, Prescaler, Timer}
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import spinal.lib.soc.pinsec.{PinsecTimerCtrl, PinsecTimerCtrlExternal}
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import spinal.lib.soc.pinsec.{PinsecTimerCtrl, PinsecTimerCtrlExternal}
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import vexriscv.plugin._
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import vexriscv.plugin._
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import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
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import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
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import spinal.lib.com.spi.ddr._
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import scala.collection.mutable.ArrayBuffer
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import scala.collection.mutable.ArrayBuffer
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/**
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/**
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@ -38,10 +39,21 @@ case class MuraxConfig(coreFrequency : HertzNumber,
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pipelineApbBridge : Boolean,
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pipelineApbBridge : Boolean,
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gpioWidth : Int,
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gpioWidth : Int,
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uartCtrlConfig : UartCtrlMemoryMappedConfig,
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uartCtrlConfig : UartCtrlMemoryMappedConfig,
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xipConfig : SpiDdrMasterCtrl.MemoryMappingParameters,
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cpuPlugins : ArrayBuffer[Plugin[VexRiscv]]){
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cpuPlugins : ArrayBuffer[Plugin[VexRiscv]]){
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require(pipelineApbBridge || pipelineMainBus, "At least pipelineMainBus or pipelineApbBridge should be enable to avoid wipe transactions")
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require(pipelineApbBridge || pipelineMainBus, "At least pipelineMainBus or pipelineApbBridge should be enable to avoid wipe transactions")
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val genXpi = xipConfig != null
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def addXip(): MuraxConfig = copy(xipConfig = SpiDdrMasterCtrl.MemoryMappingParameters(
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SpiDdrMasterCtrl.Parameters(8, 12, SpiDdrParameter(4, 1)).addAllMods(),
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cmdFifoDepth = 32,
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rspFifoDepth = 32,
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xip = SpiDdrMasterCtrl.XipBusParameters(addressWidth = 24, dataWidth = 32)
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))
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}
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}
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object MuraxConfig{
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object MuraxConfig{
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def default = MuraxConfig(
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def default = MuraxConfig(
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coreFrequency = 12 MHz,
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coreFrequency = 12 MHz,
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@ -51,6 +63,7 @@ object MuraxConfig{
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pipelineMainBus = false,
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pipelineMainBus = false,
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pipelineApbBridge = true,
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pipelineApbBridge = true,
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gpioWidth = 32,
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gpioWidth = 32,
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xipConfig = null,
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cpuPlugins = ArrayBuffer( //DebugPlugin added by the toplevel
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cpuPlugins = ArrayBuffer( //DebugPlugin added by the toplevel
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new IBusSimplePlugin(
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new IBusSimplePlugin(
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resetVector = 0x80000000l,
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resetVector = 0x80000000l,
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@ -146,6 +159,8 @@ case class Murax(config : MuraxConfig) extends Component{
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//Peripherals IO
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//Peripherals IO
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val gpioA = master(TriStateArray(gpioWidth bits))
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val gpioA = master(TriStateArray(gpioWidth bits))
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val uart = master(Uart())
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val uart = master(Uart())
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val xpi = ifGen(genXpi)(master(SpiDdrMaster(xipConfig.ctrl.spi)))
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}
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}
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@ -232,11 +247,13 @@ case class Murax(config : MuraxConfig) extends Component{
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//****** MainBus slaves ********
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//****** MainBus slaves ********
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val mainBusMapping = ArrayBuffer[(SimpleBus,SizeMapping)]()
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val ram = new MuraxSimpleBusRam(
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val ram = new MuraxSimpleBusRam(
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onChipRamSize = onChipRamSize,
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onChipRamSize = onChipRamSize,
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onChipRamHexFile = onChipRamHexFile,
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onChipRamHexFile = onChipRamHexFile,
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simpleBusConfig = simpleBusConfig
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simpleBusConfig = simpleBusConfig
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)
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)
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mainBusMapping += ram.io.bus -> (0x80000000l, onChipRamSize)
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val apbBridge = new MuraxSimpleBusToApbBridge(
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val apbBridge = new MuraxSimpleBusToApbBridge(
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apb3Config = Apb3Config(
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apb3Config = Apb3Config(
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@ -246,39 +263,54 @@ case class Murax(config : MuraxConfig) extends Component{
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pipelineBridge = pipelineApbBridge,
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pipelineBridge = pipelineApbBridge,
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simpleBusConfig = simpleBusConfig
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simpleBusConfig = simpleBusConfig
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)
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)
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mainBusMapping += apbBridge.io.simpleBus -> (0xF0000000l, 1 MB)
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//******** APB peripherals *********
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//******** APB peripherals *********
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val apbMapping = ArrayBuffer[(Apb3, SizeMapping)]()
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val gpioACtrl = Apb3Gpio(gpioWidth = gpioWidth)
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val gpioACtrl = Apb3Gpio(gpioWidth = gpioWidth)
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io.gpioA <> gpioACtrl.io.gpio
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io.gpioA <> gpioACtrl.io.gpio
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apbMapping += gpioACtrl.io.apb -> (0x00000, 4 kB)
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val uartCtrl = Apb3UartCtrl(uartCtrlConfig)
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val uartCtrl = Apb3UartCtrl(uartCtrlConfig)
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uartCtrl.io.uart <> io.uart
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uartCtrl.io.uart <> io.uart
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externalInterrupt setWhen(uartCtrl.io.interrupt)
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externalInterrupt setWhen(uartCtrl.io.interrupt)
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apbMapping += uartCtrl.io.apb -> (0x10000, 4 kB)
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val timer = new MuraxApb3Timer()
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val timer = new MuraxApb3Timer()
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timerInterrupt setWhen(timer.io.interrupt)
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timerInterrupt setWhen(timer.io.interrupt)
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apbMapping += timer.io.apb -> (0x20000, 4 kB)
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val xpi = ifGen(genXpi)(new Area{
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val ctrl = Apb3SpiDdrMasterCtrl(xipConfig)
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ctrl.io.spi <> io.xpi
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externalInterrupt setWhen(ctrl.io.interrupt)
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apbMapping += ctrl.io.apb -> (0x1F000, 4 kB)
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val accessBus = new SimpleBus(SimpleBusConfig(24,32))
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mainBusMapping += accessBus -> (0x90000000l, 16 MB)
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ctrl.io.xip.cmd.valid <> (accessBus.cmd.valid && !accessBus.cmd.wr)
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ctrl.io.xip.cmd.ready <> accessBus.cmd.ready
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ctrl.io.xip.cmd.payload <> accessBus.cmd.address
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ctrl.io.xip.rsp.valid <> accessBus.rsp.valid
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ctrl.io.xip.rsp.payload <> accessBus.rsp.data
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})
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//******** Memory mappings *********
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//******** Memory mappings *********
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val apbDecoder = Apb3Decoder(
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val apbDecoder = Apb3Decoder(
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master = apbBridge.io.apb,
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master = apbBridge.io.apb,
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slaves = List[(Apb3, SizeMapping)](
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slaves = apbMapping
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gpioACtrl.io.apb -> (0x00000, 4 kB),
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uartCtrl.io.apb -> (0x10000, 4 kB),
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timer.io.apb -> (0x20000, 4 kB)
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)
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)
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)
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val mainBusDecoder = new Area {
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val mainBusDecoder = new Area {
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val logic = new MuraxSimpleBusDecoder(
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val logic = new MuraxSimpleBusDecoder(
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master = mainBusArbiter.io.masterBus,
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master = mainBusArbiter.io.masterBus,
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specification = List[(SimpleBus,SizeMapping)](
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specification = mainBusMapping,
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ram.io.bus -> (0x80000000l, onChipRamSize),
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apbBridge.io.simpleBus -> (0xF0000000l, 1 MB)
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),
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pipelineMaster = pipelineMainBus
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pipelineMaster = pipelineMainBus
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)
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)
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}
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}
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@ -293,6 +325,12 @@ object Murax{
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}
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}
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}
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}
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object MuraxWithXip{
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def main(args: Array[String]) {
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SpinalVerilog(Murax(MuraxConfig.default.addXip()))
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}
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}
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object MuraxDhrystoneReady{
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object MuraxDhrystoneReady{
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def main(args: Array[String]) {
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def main(args: Array[String]) {
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SpinalVerilog(Murax(MuraxConfig.fast.copy(onChipRamSize = 256 kB)))
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SpinalVerilog(Murax(MuraxConfig.fast.copy(onChipRamSize = 256 kB)))
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@ -130,7 +130,7 @@ class MuraxSimpleBusToApbBridge(apb3Config: Apb3Config, pipelineBridge : Boolean
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}
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}
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}
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}
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class MuraxSimpleBusDecoder(master : SimpleBus, val specification : List[(SimpleBus,SizeMapping)], pipelineMaster : Boolean) extends Area{
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class MuraxSimpleBusDecoder(master : SimpleBus, val specification : Seq[(SimpleBus,SizeMapping)], pipelineMaster : Boolean) extends Area{
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val masterPipelined = SimpleBus(master.config)
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val masterPipelined = SimpleBus(master.config)
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if(!pipelineMaster) {
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if(!pipelineMaster) {
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masterPipelined.cmd << master.cmd
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masterPipelined.cmd << master.cmd
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@ -146,7 +146,7 @@ class MuraxSimpleBusDecoder(master : SimpleBus, val specification : List[(Simple
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val hits = for((slaveBus, memorySpace) <- specification) yield {
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val hits = for((slaveBus, memorySpace) <- specification) yield {
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val hit = memorySpace.hit(masterPipelined.cmd.address)
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val hit = memorySpace.hit(masterPipelined.cmd.address)
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slaveBus.cmd.valid := masterPipelined.cmd.valid && hit
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slaveBus.cmd.valid := masterPipelined.cmd.valid && hit
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slaveBus.cmd.payload := masterPipelined.cmd.payload
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slaveBus.cmd.payload := masterPipelined.cmd.payload.resized
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hit
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hit
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}
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}
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val noHit = !hits.orR
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val noHit = !hits.orR
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