dbus mmu access improvement

src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala

@@ -159,7 +159,7 @@ object VexRiscvSmpClusterGen {
                      iCacheWays : Int = 2,
                      dCacheWays : Int = 2,
                      iBusRelax : Boolean = false,
-                     earlyBranch : Boolean = true) = {
+                     earlyBranch : Boolean = false) = {
     assert(iCacheSize/iCacheWays <= 4096, "Instruction cache ways can't be bigger than 4096 bytes")
     assert(dCacheSize/dCacheWays <= 4096, "Data cache ways can't be bigger than 4096 bytes")
     val config = VexRiscvConfig(

src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala

@@ -250,8 +250,10 @@ class DBusCachedPlugin(val config : DataCacheConfig,
       if(twoStageMmu) {
         mmuBus.cmd(0).isValid := cache.io.cpu.execute.isValid
         mmuBus.cmd(0).isStuck := arbitration.isStuck
-        mmuBus.cmd(0).virtualAddress := cache.io.cpu.execute.address
+        mmuBus.cmd(0).virtualAddress := input(SRC_ADD).asUInt
         mmuBus.cmd(0).bypassTranslation := False
+//        KeepAttribute(mmuBus.cmd(0))
+//        KeepAttribute(mmuBus.cmd(1))
       }
 
       cache.io.cpu.flush.valid := arbitration.isValid && input(MEMORY_MANAGMENT)

src/main/scala/vexriscv/plugin/SrcPlugin.scala

@@ -2,6 +2,7 @@ package vexriscv.plugin
 
 import vexriscv._
 import spinal.core._
+import spinal.lib.KeepAttribute
 
 
 class SrcPlugin(separatedAddSub : Boolean = false, executeInsertion : Boolean = false, decodeAddSub : Boolean = false) extends Plugin[VexRiscv]{