dbus mmu access improvement

This commit is contained in:
Dolu1990 2020-09-17 22:06:29 +02:00
parent de820daf74
commit 3f5e771a5c
3 changed files with 5 additions and 2 deletions

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@ -159,7 +159,7 @@ object VexRiscvSmpClusterGen {
iCacheWays : Int = 2, iCacheWays : Int = 2,
dCacheWays : Int = 2, dCacheWays : Int = 2,
iBusRelax : Boolean = false, iBusRelax : Boolean = false,
earlyBranch : Boolean = true) = { earlyBranch : Boolean = false) = {
assert(iCacheSize/iCacheWays <= 4096, "Instruction cache ways can't be bigger than 4096 bytes") assert(iCacheSize/iCacheWays <= 4096, "Instruction cache ways can't be bigger than 4096 bytes")
assert(dCacheSize/dCacheWays <= 4096, "Data cache ways can't be bigger than 4096 bytes") assert(dCacheSize/dCacheWays <= 4096, "Data cache ways can't be bigger than 4096 bytes")
val config = VexRiscvConfig( val config = VexRiscvConfig(

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@ -250,8 +250,10 @@ class DBusCachedPlugin(val config : DataCacheConfig,
if(twoStageMmu) { if(twoStageMmu) {
mmuBus.cmd(0).isValid := cache.io.cpu.execute.isValid mmuBus.cmd(0).isValid := cache.io.cpu.execute.isValid
mmuBus.cmd(0).isStuck := arbitration.isStuck mmuBus.cmd(0).isStuck := arbitration.isStuck
mmuBus.cmd(0).virtualAddress := cache.io.cpu.execute.address mmuBus.cmd(0).virtualAddress := input(SRC_ADD).asUInt
mmuBus.cmd(0).bypassTranslation := False mmuBus.cmd(0).bypassTranslation := False
// KeepAttribute(mmuBus.cmd(0))
// KeepAttribute(mmuBus.cmd(1))
} }
cache.io.cpu.flush.valid := arbitration.isValid && input(MEMORY_MANAGMENT) cache.io.cpu.flush.valid := arbitration.isValid && input(MEMORY_MANAGMENT)

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@ -2,6 +2,7 @@ package vexriscv.plugin
import vexriscv._ import vexriscv._
import spinal.core._ import spinal.core._
import spinal.lib.KeepAttribute
class SrcPlugin(separatedAddSub : Boolean = false, executeInsertion : Boolean = false, decodeAddSub : Boolean = false) extends Plugin[VexRiscv]{ class SrcPlugin(separatedAddSub : Boolean = false, executeInsertion : Boolean = false, decodeAddSub : Boolean = false) extends Plugin[VexRiscv]{