dbus mmu access improvement
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@ -159,7 +159,7 @@ object VexRiscvSmpClusterGen {
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iCacheWays : Int = 2,
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iCacheWays : Int = 2,
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dCacheWays : Int = 2,
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dCacheWays : Int = 2,
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iBusRelax : Boolean = false,
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iBusRelax : Boolean = false,
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earlyBranch : Boolean = true) = {
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earlyBranch : Boolean = false) = {
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assert(iCacheSize/iCacheWays <= 4096, "Instruction cache ways can't be bigger than 4096 bytes")
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assert(iCacheSize/iCacheWays <= 4096, "Instruction cache ways can't be bigger than 4096 bytes")
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assert(dCacheSize/dCacheWays <= 4096, "Data cache ways can't be bigger than 4096 bytes")
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assert(dCacheSize/dCacheWays <= 4096, "Data cache ways can't be bigger than 4096 bytes")
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val config = VexRiscvConfig(
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val config = VexRiscvConfig(
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@ -250,8 +250,10 @@ class DBusCachedPlugin(val config : DataCacheConfig,
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if(twoStageMmu) {
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if(twoStageMmu) {
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mmuBus.cmd(0).isValid := cache.io.cpu.execute.isValid
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mmuBus.cmd(0).isValid := cache.io.cpu.execute.isValid
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mmuBus.cmd(0).isStuck := arbitration.isStuck
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mmuBus.cmd(0).isStuck := arbitration.isStuck
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mmuBus.cmd(0).virtualAddress := cache.io.cpu.execute.address
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mmuBus.cmd(0).virtualAddress := input(SRC_ADD).asUInt
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mmuBus.cmd(0).bypassTranslation := False
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mmuBus.cmd(0).bypassTranslation := False
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// KeepAttribute(mmuBus.cmd(0))
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// KeepAttribute(mmuBus.cmd(1))
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}
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}
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cache.io.cpu.flush.valid := arbitration.isValid && input(MEMORY_MANAGMENT)
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cache.io.cpu.flush.valid := arbitration.isValid && input(MEMORY_MANAGMENT)
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@ -2,6 +2,7 @@ package vexriscv.plugin
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import vexriscv._
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import vexriscv._
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import spinal.core._
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import spinal.core._
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import spinal.lib.KeepAttribute
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class SrcPlugin(separatedAddSub : Boolean = false, executeInsertion : Boolean = false, decodeAddSub : Boolean = false) extends Plugin[VexRiscv]{
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class SrcPlugin(separatedAddSub : Boolean = false, executeInsertion : Boolean = false, decodeAddSub : Boolean = false) extends Plugin[VexRiscv]{
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