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VexRiscv
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Dolu1990 2018-01-28 13:04:59 +01:00 committed by GitHub
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@ -91,7 +91,7 @@ VexRiscv full with MMU (RV32IM, 1.17 DMIPS/Mhz with cache trashing, 4KB-I$, 4KB-
Cyclone II -> 94 Mhz 3,187 LUT 2,281 FF
```
There is the a summary of the configuration which produce 1.29 DMIPS :
There is a summary of the configuration which produce 1.29 DMIPS :
- 5 stage : F -> D -> E -> M -> WB
- single cycle ADD/SUB/Bitwise/Shift ALU