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fix withStall

This commit is contained in:
Dolu1990 2020-04-21 21:20:54 +02:00
parent 3885e52bb7
commit 3fb123a64a
1 changed files with 3 additions and 4 deletions
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7
src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
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@ -8,7 +8,6 @@ import spinal.lib.bus.bmb.sim.BmbMemoryAgent
import spinal.lib.bus.bmb.{Bmb, BmbArbiter, BmbDecoder, BmbExclusiveMonitor, BmbInvalidateMonitor, BmbParameter} import spinal.lib.bus.bmb.{Bmb, BmbArbiter, BmbDecoder, BmbExclusiveMonitor, BmbInvalidateMonitor, BmbParameter}
import spinal.lib.com.jtag.Jtag import spinal.lib.com.jtag.Jtag
import spinal.lib.com.jtag.sim.JtagTcp import spinal.lib.com.jtag.sim.JtagTcp
import vexriscv.demo.smp.VexRiscvSmpClusterTest.{cpuCount, withStall}
import vexriscv.ip.{DataCacheAck, DataCacheConfig, DataCacheMemBus, InstructionCacheConfig} import vexriscv.ip.{DataCacheAck, DataCacheConfig, DataCacheMemBus, InstructionCacheConfig}
import vexriscv.plugin.{BranchPlugin, CsrPlugin, CsrPluginConfig, DBusCachedPlugin, DBusSimplePlugin, DebugPlugin, DecoderSimplePlugin, FullBarrelShifterPlugin, HazardSimplePlugin, IBusCachedPlugin, IBusSimplePlugin, IntAluPlugin, MmuPlugin, MmuPortConfig, MulDivIterativePlugin, MulPlugin, RegFilePlugin, STATIC, SrcPlugin, YamlPlugin} import vexriscv.plugin.{BranchPlugin, CsrPlugin, CsrPluginConfig, DBusCachedPlugin, DBusSimplePlugin, DebugPlugin, DecoderSimplePlugin, FullBarrelShifterPlugin, HazardSimplePlugin, IBusCachedPlugin, IBusSimplePlugin, IntAluPlugin, MmuPlugin, MmuPortConfig, MulDivIterativePlugin, MulPlugin, RegFilePlugin, STATIC, SrcPlugin, YamlPlugin}
import vexriscv.{Riscv, VexRiscv, VexRiscvConfig, plugin} import vexriscv.{Riscv, VexRiscv, VexRiscvConfig, plugin}
@ -301,7 +300,7 @@ object VexRiscvSmpClusterTestInfrastructure{
val CLINT_CMP_ADDR = CLINT_ADDR+0x4000 val CLINT_CMP_ADDR = CLINT_ADDR+0x4000
val CLINT_TIME_ADDR = CLINT_ADDR+0xBFF8 val CLINT_TIME_ADDR = CLINT_ADDR+0xBFF8
def ram(dut : VexRiscvSmpCluster) = { def ram(dut : VexRiscvSmpCluster, withStall : Boolean) = {
import spinal.core.sim._ import spinal.core.sim._
val cpuCount = dut.cpus.size val cpuCount = dut.cpus.size
val ram = new BmbMemoryAgent(0x100000000l){ val ram = new BmbMemoryAgent(0x100000000l){
@ -479,7 +478,7 @@ object VexRiscvSmpClusterTest extends App{
SimTimeout(100000000l*10*cpuCount) SimTimeout(100000000l*10*cpuCount)
dut.clockDomain.forkSimSpeedPrinter(1.0) dut.clockDomain.forkSimSpeedPrinter(1.0)
VexRiscvSmpClusterTestInfrastructure.init(dut) VexRiscvSmpClusterTestInfrastructure.init(dut)
val ram = VexRiscvSmpClusterTestInfrastructure.ram(dut) val ram = VexRiscvSmpClusterTestInfrastructure.ram(dut, withStall)
ram.memory.loadBin(0x80000000l, "src/test/cpp/raw/smp/build/smp.bin") ram.memory.loadBin(0x80000000l, "src/test/cpp/raw/smp/build/smp.bin")
periodicaly(20000*10){ periodicaly(20000*10){
assert(ram.reportWatchdog != 0) assert(ram.reportWatchdog != 0)
@ -505,7 +504,7 @@ object VexRiscvSmpClusterOpenSbi extends App{
simConfig.workspaceName("rawr_4c").compile(VexRiscvSmpClusterGen.vexRiscvCluster(cpuCount)).doSimUntilVoid(seed = 42){dut => simConfig.workspaceName("rawr_4c").compile(VexRiscvSmpClusterGen.vexRiscvCluster(cpuCount)).doSimUntilVoid(seed = 42){dut =>
// dut.clockDomain.forkSimSpeedPrinter(1.0) // dut.clockDomain.forkSimSpeedPrinter(1.0)
VexRiscvSmpClusterTestInfrastructure.init(dut) VexRiscvSmpClusterTestInfrastructure.init(dut)
val ram = VexRiscvSmpClusterTestInfrastructure.ram(dut) val ram = VexRiscvSmpClusterTestInfrastructure.ram(dut, withStall)
// ram.memory.loadBin(0x80000000l, "../opensbi/build/platform/spinal/vexriscv/sim/smp/firmware/fw_payload.bin") // ram.memory.loadBin(0x80000000l, "../opensbi/build/platform/spinal/vexriscv/sim/smp/firmware/fw_payload.bin")
ram.memory.loadBin(0x80000000l, "../opensbi/build/platform/spinal/vexriscv/sim/smp/firmware/fw_jump.bin") ram.memory.loadBin(0x80000000l, "../opensbi/build/platform/spinal/vexriscv/sim/smp/firmware/fw_jump.bin")
ram.memory.loadBin(0xC0000000l, "../buildroot/output/images/Image") ram.memory.loadBin(0xC0000000l, "../buildroot/output/images/Image")