fix withStall
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parent
3885e52bb7
commit
3fb123a64a
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@ -8,7 +8,6 @@ import spinal.lib.bus.bmb.sim.BmbMemoryAgent
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import spinal.lib.bus.bmb.{Bmb, BmbArbiter, BmbDecoder, BmbExclusiveMonitor, BmbInvalidateMonitor, BmbParameter}
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import spinal.lib.com.jtag.Jtag
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import spinal.lib.com.jtag.sim.JtagTcp
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import vexriscv.demo.smp.VexRiscvSmpClusterTest.{cpuCount, withStall}
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import vexriscv.ip.{DataCacheAck, DataCacheConfig, DataCacheMemBus, InstructionCacheConfig}
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import vexriscv.plugin.{BranchPlugin, CsrPlugin, CsrPluginConfig, DBusCachedPlugin, DBusSimplePlugin, DebugPlugin, DecoderSimplePlugin, FullBarrelShifterPlugin, HazardSimplePlugin, IBusCachedPlugin, IBusSimplePlugin, IntAluPlugin, MmuPlugin, MmuPortConfig, MulDivIterativePlugin, MulPlugin, RegFilePlugin, STATIC, SrcPlugin, YamlPlugin}
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import vexriscv.{Riscv, VexRiscv, VexRiscvConfig, plugin}
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@ -301,7 +300,7 @@ object VexRiscvSmpClusterTestInfrastructure{
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val CLINT_CMP_ADDR = CLINT_ADDR+0x4000
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val CLINT_TIME_ADDR = CLINT_ADDR+0xBFF8
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def ram(dut : VexRiscvSmpCluster) = {
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def ram(dut : VexRiscvSmpCluster, withStall : Boolean) = {
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import spinal.core.sim._
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val cpuCount = dut.cpus.size
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val ram = new BmbMemoryAgent(0x100000000l){
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@ -479,7 +478,7 @@ object VexRiscvSmpClusterTest extends App{
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SimTimeout(100000000l*10*cpuCount)
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dut.clockDomain.forkSimSpeedPrinter(1.0)
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VexRiscvSmpClusterTestInfrastructure.init(dut)
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val ram = VexRiscvSmpClusterTestInfrastructure.ram(dut)
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val ram = VexRiscvSmpClusterTestInfrastructure.ram(dut, withStall)
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ram.memory.loadBin(0x80000000l, "src/test/cpp/raw/smp/build/smp.bin")
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periodicaly(20000*10){
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assert(ram.reportWatchdog != 0)
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@ -505,7 +504,7 @@ object VexRiscvSmpClusterOpenSbi extends App{
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simConfig.workspaceName("rawr_4c").compile(VexRiscvSmpClusterGen.vexRiscvCluster(cpuCount)).doSimUntilVoid(seed = 42){dut =>
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// dut.clockDomain.forkSimSpeedPrinter(1.0)
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VexRiscvSmpClusterTestInfrastructure.init(dut)
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val ram = VexRiscvSmpClusterTestInfrastructure.ram(dut)
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val ram = VexRiscvSmpClusterTestInfrastructure.ram(dut, withStall)
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// ram.memory.loadBin(0x80000000l, "../opensbi/build/platform/spinal/vexriscv/sim/smp/firmware/fw_payload.bin")
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ram.memory.loadBin(0x80000000l, "../opensbi/build/platform/spinal/vexriscv/sim/smp/firmware/fw_jump.bin")
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ram.memory.loadBin(0xC0000000l, "../buildroot/output/images/Image")
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