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VexRiscv
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FreeRTOS tested 

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This commit is contained in:
Charles Papon 2017-03-25 16:44:42 +01:00
parent 9bbf3ee3e7
commit 4000191966
11 changed files with 2626 additions and 44 deletions
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2
src/main/scala/SpinalRiscv/Pipeline.scala
View File

@ -110,7 +110,7 @@ trait Pipeline {
}
for(stageIndex <- 0 until stages.length; stage = stages(stageIndex)){
stage.arbitration.isStuckByOthers := stages.takeRight(stages.length - stageIndex - 1).map(s => s.arbitration.haltIt && !s.arbitration.removeIt).foldLeft(False)(_ || _)
stage.arbitration.isStuckByOthers := stages.takeRight(stages.length - stageIndex - 1).map(s => s.arbitration.haltIt/* && !s.arbitration.removeIt*/).foldLeft(False)(_ || _)
stage.arbitration.isStuck := stage.arbitration.haltIt || stage.arbitration.isStuckByOthers
stage.arbitration.isFiring := stage.arbitration.isValid && !stage.arbitration.isStuck && !stage.arbitration.removeIt
}

7
src/main/scala/SpinalRiscv/Plugin/BranchPlugin.scala
View File

@ -112,9 +112,7 @@ class BranchPlugin(earlyBranch : Boolean,prediction : BranchPrediction,historyRa
jumpInterface.payload := input(BRANCH_CALC)
when(jumpInterface.valid) {
fetch.arbitration.removeIt := True
decode.arbitration.removeIt := True
if(!earlyBranch) execute.arbitration.removeIt := True
stages(indexOf(branchStage) - 1).arbitration.flushIt := True
}
}
}
@ -210,9 +208,6 @@ class BranchPlugin(earlyBranch : Boolean,prediction : BranchPrediction,historyRa
when(jumpInterface.valid) {
stages(indexOf(branchStage) - 1).arbitration.flushIt := True
// fetch.arbitration.removeIt := True
// decode.arbitration.removeIt := True
// if(!earlyBranch) execute.arbitration.removeIt := True
}
}

5
src/main/scala/SpinalRiscv/Plugin/DBusSimplePlugin.scala
View File

@ -30,6 +30,8 @@ class DBusSimplePlugin extends Plugin[VexRiscv]{
object MEMORY_READ_DATA extends Stageable(Bits(32 bits))
object MEMORY_ADDRESS_LOW extends Stageable(UInt(2 bits))
override def setup(pipeline: VexRiscv): Unit = {
import Riscv._
import pipeline.config._
@ -69,6 +71,9 @@ class DBusSimplePlugin extends Plugin[VexRiscv]{
SW -> (storeActions)
))
// val exceptionService = pipeline.service(classOf[ExceptionService])
// executeExceptionPort = exceptionService.newExceptionPort(pipeline.execute)
}
override def build(pipeline: VexRiscv): Unit = {

49
src/main/scala/SpinalRiscv/Plugin/MachineCsr.scala
View File

@ -35,7 +35,9 @@ case class MachineCsrConfig(
mcauseAccess : CsrAccess,
mbadaddrAccess : CsrAccess,
mcycleAccess : CsrAccess,
minstretAccess : CsrAccess
minstretAccess : CsrAccess,
wfiGen : Boolean,
ecallGen : Boolean
)
@ -81,7 +83,9 @@ class MachineCsr(config : MachineCsrConfig) extends Plugin[VexRiscv] with Except
var externalInterrupt : Bool = null
object EnvCtrlEnum extends SpinalEnum(binarySequential){
val NONE, EBREAK, ECALL, MRET = newElement()
val NONE, EBREAK, MRET= newElement()
val WFI = if(wfiGen) newElement() else null
val ECALL = if(ecallGen) newElement() else null
}
object ENV_CTRL extends Stageable(EnvCtrlEnum())
@ -122,20 +126,22 @@ class MachineCsr(config : MachineCsrConfig) extends Plugin[VexRiscv] with Except
CSRRWI -> immediatActions,
CSRRSI -> immediatActions,
CSRRCI -> immediatActions,
ECALL -> (defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.ECALL)),
EBREAK -> (defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.EBREAK)),
// EBREAK -> (defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.EBREAK)), //TODO
MRET -> (defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.MRET))
))
if(wfiGen) decoderService.add(WFI, defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.WFI))
if(ecallGen) decoderService.add(ECALL, defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.ECALL))
val pcManagerService = pipeline.service(classOf[JumpService])
jumpInterface = pcManagerService.createJumpInterface(pipeline.execute)
jumpInterface.valid := False
jumpInterface.payload.assignDontCare()
if(ecallGen) {
pluginExceptionPort = newExceptionPort(pipeline.execute)
pluginExceptionPort.valid := False
pluginExceptionPort.payload.assignDontCare()
}
timerInterrupt = in Bool() setName("timerInterrupt")
externalInterrupt = in Bool() setName("externalInterrupt")
@ -227,16 +233,10 @@ class MachineCsr(config : MachineCsrConfig) extends Plugin[VexRiscv] with Except
val pipelineLiberator = new Area{
val enable = False
prefetch.arbitration.haltIt setWhen(enable)
val done = ! List(fetch, decode, execute, memory, writeBack).map(_.arbitration.isValid).orR
val done = ! List(fetch, decode, execute, memory).map(_.arbitration.isValid).orR
}
//Manage ECALL instructions
when(execute.arbitration.isValid && execute.input(ENV_CTRL) === EnvCtrlEnum.ECALL){
pluginExceptionPort.valid := True
pluginExceptionPort.exceptionCode := 11
}
//Aggregate all exception port and remove required instructions
val exceptionPortCtrl = if(exceptionPortsInfos.nonEmpty) new Area{
@ -245,6 +245,7 @@ class MachineCsr(config : MachineCsrConfig) extends Plugin[VexRiscv] with Except
decode.arbitration.haltIt setWhen(pipelineHasException)
val groupedByStage = exceptionPortsInfos.map(_.stage).distinct.map(s => {
assert(s != writeBack)
val stagePortsInfos = exceptionPortsInfos.filter(_.stage == s)
val stagePort = stagePortsInfos.length match{
case 1 => stagePortsInfos.head.port
@ -276,7 +277,7 @@ class MachineCsr(config : MachineCsrConfig) extends Plugin[VexRiscv] with Except
val interrupt = ((mip.MSIP && mie.MSIE) || (mip.MEIP && mie.MEIE) || (mip.MTIP && mie.MTIE)) && mstatus.MIE
val exception = if(exceptionPortsInfos.nonEmpty) writeBack.arbitration.isValid && writeBack.input(EXCEPTION) else False
val writeBackWfi = if(wfiGen) writeBack.arbitration.isValid && writeBack.input(ENV_CTRL) === EnvCtrlEnum.WFI else False
//Interrupt/Exception entry logic
pipelineLiberator.enable setWhen interrupt
@ -285,17 +286,20 @@ class MachineCsr(config : MachineCsrConfig) extends Plugin[VexRiscv] with Except
jumpInterface.payload := mtvec
mstatus.MIE := False
mstatus.MPIE := mstatus.MIE
mepc := exception ? writeBack.input(PC) | prefetch.input(PC_CALC_WITHOUT_JUMP)
mepc := exception mux(
True -> writeBack.input(PC),
False -> (writeBackWfi ? (writeBack.input(PC) + 4) | prefetch.input(PC_CALC_WITHOUT_JUMP)) //TODO ? WFI could emulate J PC + 4
)
mcause.interrupt := interrupt
mcause.exceptionCode := interrupt.mux(
True -> ((mip.MEIP && mie.MEIE) ? U(11) | ((mip.MSIP && mie.MSIE) ? U(3) | U(7))),
False -> writeBack.input(EXCEPTION_CAUSE).exceptionCode
False -> (if(exceptionPortCtrl != null) writeBack.input(EXCEPTION_CAUSE).exceptionCode else U(0))
)
}
//Interrupt/Exception exit logic
//Manage MRET instructions
when(memory.arbitration.isFiring && memory.input(ENV_CTRL) === EnvCtrlEnum.MRET){
jumpInterface.valid := True
jumpInterface.payload := mepc
@ -303,6 +307,19 @@ class MachineCsr(config : MachineCsrConfig) extends Plugin[VexRiscv] with Except
mstatus.MIE := mstatus.MPIE
}
//Manage ECALL instructions
if(ecallGen) when(execute.arbitration.isValid && execute.input(ENV_CTRL) === EnvCtrlEnum.ECALL){
pluginExceptionPort.valid := True
pluginExceptionPort.exceptionCode := 11
}
//Manage WFI instructions
if(wfiGen) when(execute.arbitration.isValid && execute.input(ENV_CTRL) === EnvCtrlEnum.WFI){
when(!interrupt){
execute.arbitration.haltIt := True
decode.arbitration.flushIt := True
}
}
//CSR read/write instructions management
execute plug new Area {

1
src/main/scala/SpinalRiscv/Riscv.scala
View File

@ -83,6 +83,7 @@ object Riscv{
def ECALL = M"00000000000000000000000001110011"
def EBREAK = M"00000000000100000000000001110011"
def MRET = M"00110000001000000000000001110011"
def WFI = M"00010000010100000000000001110011"
object CSR{
def MVENDORID = 0xF11 // MRO Vendor ID.

34
src/main/scala/SpinalRiscv/TopLevel.scala
View File

@ -31,24 +31,42 @@ object TopLevel {
)
import CsrAccess._
val csrConfig = MachineCsrConfig(
mvendorid = 11,
marchid = 22,
mimpid = 33,
mhartid = 0,
misaExtensionsInit = 66,
misaAccess = READ_WRITE,
mtvecAccess = READ_WRITE,
misaAccess = CsrAccess.READ_WRITE,
mtvecAccess = CsrAccess.READ_WRITE,
mtvecInit = 0x00000020l,
mepcAccess = READ_WRITE,
mepcAccess = CsrAccess.READ_WRITE,
mscratchGen = true,
mcauseAccess = READ_WRITE,
mbadaddrAccess = READ_WRITE,
mcycleAccess = READ_WRITE,
minstretAccess = READ_WRITE
mcauseAccess = CsrAccess.READ_WRITE,
mbadaddrAccess = CsrAccess.READ_WRITE,
mcycleAccess = CsrAccess.READ_WRITE,
minstretAccess = CsrAccess.READ_WRITE,
ecallGen = false,
wfiGen = false
)
// val csrConfig = MachineCsrConfig(
// mvendorid = null,
// marchid = null,
// mimpid = null,
// mhartid = null,
// misaExtensionsInit = 66,
// misaAccess = CsrAccess.NONE,
// mtvecAccess = CsrAccess.NONE,
// mtvecInit = 0x00000020l,
// mepcAccess = CsrAccess.READ_ONLY,
// mscratchGen = false,
// mcauseAccess = CsrAccess.READ_ONLY,
// mbadaddrAccess = CsrAccess.NONE,
// mcycleAccess = CsrAccess.NONE,
// minstretAccess = CsrAccess.NONE
// )
config.plugins ++= List(
new PcManagerSimplePlugin(0x00000000l, false),
new IBusSimplePlugin(true),

100
src/test/cpp/testA/default.gtkw Normal file
View File

@ -0,0 +1,100 @@
[*]
[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI
[*] Sat Mar 25 13:21:38 2017
[*]
[dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/testA/machineCsr.vcd"
[dumpfile_mtime] "Sat Mar 25 13:21:31 2017"
[dumpfile_size] 2048473
[savefile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/testA/default.gtkw"
[timestart] 0
[size] 1776 953
[pos] -1 -1
*-9.770813 718 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] TOP.
[treeopen] TOP.VexRiscv.
[sst_width] 294
[signals_width] 597
[sst_expanded] 1
[sst_vpaned_height] 593
@28
TOP.VexRiscv.writeBack_arbitration_isValid
@22
TOP.VexRiscv.writeBack_PC[31:0]
TOP.VexRiscv.writeBack_INSTRUCTION[31:0]
TOP.VexRiscv.RegFilePlugin_regFile(10)[31:0]
TOP.VexRiscv.RegFilePlugin_regFile(11)[31:0]
TOP.VexRiscv.prefetch_PcManagerSimplePlugin_pcBeforeJumps[31:0]
TOP.VexRiscv.prefetch_PcManagerSimplePlugin_pc[31:0]
TOP.VexRiscv.MachineCsr_mepc[31:0]
@28
TOP.VexRiscv.timerInterrupt
TOP.VexRiscv.execute_arbitration_isValid
@22
TOP.VexRiscv.execute_PC[31:0]
@28
TOP.VexRiscv.MachineCsr_mie_MEIE
TOP.VexRiscv.MachineCsr_mie_MSIE
TOP.VexRiscv.MachineCsr_mie_MTIE
TOP.VexRiscv.MachineCsr_mstatus_MIE
TOP.VexRiscv.MachineCsr_mip_MEIP
TOP.VexRiscv.MachineCsr_mip_MSIP
TOP.VexRiscv.MachineCsr_mip_MTIP
TOP.VexRiscv.MachineCsr_interrupt
TOP.VexRiscv.MachineCsr_writeBackWfi
TOP.VexRiscv.writeBack_arbitration_isValid
TOP.VexRiscv.writeBack_ENV_CTRL[2:0]
TOP.VexRiscv.execute_EXCEPTION
TOP.VexRiscv.memory_EXCEPTION
TOP.VexRiscv.writeBack_EXCEPTION
TOP.VexRiscv.prefetch_arbitration_isValid
TOP.VexRiscv.fetch_arbitration_isValid
TOP.VexRiscv.decode_arbitration_isValid
TOP.VexRiscv.execute_arbitration_isValid
TOP.VexRiscv.memory_arbitration_isValid
TOP.VexRiscv.writeBack_arbitration_isValid
TOP.VexRiscv.prefetch_arbitration_removeIt
TOP.VexRiscv.fetch_arbitration_removeIt
@29
TOP.VexRiscv.decode_arbitration_removeIt
@28
TOP.VexRiscv.execute_arbitration_removeIt
TOP.VexRiscv.memory_arbitration_removeIt
TOP.VexRiscv.writeBack_arbitration_removeIt
TOP.VexRiscv.prefetch_arbitration_isStuck
TOP.VexRiscv.fetch_arbitration_isStuck
TOP.VexRiscv.decode_arbitration_isStuck
TOP.VexRiscv.execute_arbitration_isStuck
TOP.VexRiscv.memory_arbitration_isStuck
TOP.VexRiscv.writeBack_arbitration_isStuck
@22
TOP.VexRiscv.prefetch_PcManagerSimplePlugin_jump_pcLoad_payload[31:0]
@28
TOP.VexRiscv.prefetch_PcManagerSimplePlugin_jump_pcLoad_valid
@22
TOP.VexRiscv.MachineCsr_mepc[31:0]
TOP.VexRiscv.prefetch_PcManagerSimplePlugin_pcReg[31:0]
TOP.VexRiscv.prefetch_PC_CALC_WITHOUT_JUMP[31:0]
TOP.VexRiscv.prefetch_PcManagerSimplePlugin_pc[31:0]
TOP.VexRiscv.prefetch_PC[31:0]
TOP.VexRiscv.fetch_PC[31:0]
TOP.VexRiscv.decode_PC[31:0]
TOP.VexRiscv.execute_PC[31:0]
TOP.VexRiscv.memory_PC[31:0]
TOP.VexRiscv.writeBack_PC[31:0]
@28
TOP.VexRiscv.prefetch_arbitration_isStuckByOthers
TOP.VexRiscv.fetch_arbitration_isStuckByOthers
TOP.VexRiscv.decode_arbitration_isStuckByOthers
TOP.VexRiscv.execute_arbitration_isStuckByOthers
TOP.VexRiscv.memory_arbitration_isStuckByOthers
TOP.VexRiscv.writeBack_arbitration_isStuckByOthers
TOP.VexRiscv.prefetch_arbitration_haltIt
TOP.VexRiscv.fetch_arbitration_haltIt
TOP.VexRiscv.decode_arbitration_haltIt
TOP.VexRiscv.execute_arbitration_haltIt
TOP.VexRiscv.memory_arbitration_haltIt
TOP.VexRiscv.writeBack_arbitration_haltIt
TOP.VexRiscv.MachineCsr_mie_MTIE
TOP.VexRiscv.MachineCsr_mip_MTIP
[pattern_trace] 1
[pattern_trace] 0

28
src/test/cpp/testA/main.cpp
View File

@ -137,6 +137,7 @@ public:
string name;
VVexRiscv* top;
int i;
uint32_t bootPc = -1;
uint32_t iStall = 1,dStall = 1;
#ifdef TRACE
VerilatedVcdC* tfp;
@ -171,17 +172,21 @@ public:
return this;
}
Workspace* bootAt(uint32_t pc) { bootPc = pc;}
virtual void postReset() {}
virtual void checks(){}
virtual void pass(){ throw success();}
virtual void fail(){ throw std::exception();}
void dump(int i){
#ifdef TRACE
tfp->dump(i);
if(i/2 >= TRACE_START) tfp->dump(i);
#endif
}
Workspace* run(uint32_t timeout = 5000){
// cout << "Start " << name << endl;
uint64_t mTimeCmp = 0;
uint64_t mTime = 0;
currentTime = 4;
// init trace dump
Verilated::traceEverOn(true);
@ -200,7 +205,7 @@ public:
top->reset = 1;
top->eval();
#ifdef CSR
top->timerInterrupt = 1;
top->timerInterrupt = 0;
top->externalInterrupt = 1;
#endif
dump(0);
@ -209,10 +214,16 @@ public:
top->clk = 1;
postReset();
if(bootPc != -1) top->VexRiscv->prefetch_PcManagerSimplePlugin_pcReg = bootPc;
try {
// run simulation for 100 clock periods
for (i = 16; i < timeout*2; i+=2) {
mTime = i/2;
#ifdef CSR
top->timerInterrupt = mTime >= mTimeCmp ? 1 : 0;
//if(mTime == mTimeCmp) printf("SIM timer tick\n");
#endif
currentTime = i;
uint32_t iRsp_inst_next = top->iRsp_inst;
uint32_t dRsp_inst_next = VL_RANDOM_I(32);
@ -251,6 +262,8 @@ public:
break;
}
case 0xF00FFF20u: pass(); break;
case 0xF00FFF48u: mTimeCmp = (mTimeCmp & 0xFFFFFFFF00000000) | top->dCmd_payload_data;break;
case 0xF00FFF4Cu: mTimeCmp = (mTimeCmp & 0x00000000FFFFFFFF) | (((uint64_t)top->dCmd_payload_data) << 32); /*cout << "mTimeCmp <= " << mTimeCmp << endl; */break;
}
}else{
for(uint32_t b = 0;b < (1 << top->dCmd_payload_size);b++){
@ -262,6 +275,10 @@ public:
case 0xF00FFF10u:
dRsp_inst_next = i/2;
break;
case 0xF00FFF40u: dRsp_inst_next = mTime; break;
case 0xF00FFF44u: dRsp_inst_next = mTime >> 32; break;
case 0xF00FFF48u: dRsp_inst_next = mTimeCmp; break;
case 0xF00FFF4Cu: dRsp_inst_next = mTimeCmp >> 32; break;
}
memTraces << (currentTime
#ifdef REF
@ -385,13 +402,13 @@ class RiscvTest : public Workspace{
public:
RiscvTest(string name) : Workspace(name) {
loadHex("../../resources/hex/" + name + ".hex");
bootAt(0x800000bcu);
}
virtual void postReset() {
// #ifdef CSR
// top->VexRiscv->prefetch_PcManagerSimplePlugin_pcReg = 0x80000000u;
// #else
top->VexRiscv->prefetch_PcManagerSimplePlugin_pcReg = 0x800000bcu;
// #endif
}
@ -550,7 +567,7 @@ int main(int argc, char **argv, char **env) {
#endif
#ifdef CSR
uint32_t machineCsrRef[] = {1,11, 2,0x80000003u, 3,0x80000007u, 4,0x8000000bu, 5};
uint32_t machineCsrRef[] = {1,11, 2,0x80000003u, 3,0x80000007u, 4,0x8000000bu, 5,6,7,0x80000007u ,8};
redo(REDO,TestX28("machineCsr",machineCsrRef, sizeof(machineCsrRef)/4).run(2e3);)
#endif
@ -563,6 +580,9 @@ int main(int argc, char **argv, char **env) {
#endif
#ifdef CSR
redo(REDO,Workspace("freeRTOS_demo").loadHex("../../resources/hex/freeRTOS_demo.hex")->bootAt(0x80000000u)->run(100e6);)
#endif
}
uint64_t duration = timer_end(startedAt);

9
src/test/cpp/testA/makefile
View File

@ -1,7 +1,8 @@
TRACE=yes
TRACE=no
TRACE_START=0
CSR=yes
DHRYSTONE=no
REDO=1
DHRYSTONE=yes
REDO=5
ADDCFLAGS += -CFLAGS -DREDO=${REDO}
ifeq ($(DHRYSTONE),yes)
@ -17,6 +18,8 @@ ifeq ($(CSR),yes)
ADDCFLAGS += -CFLAGS -DCSR
endif
ADDCFLAGS += -CFLAGS -DTRACE_START=${TRACE_START}
run: compile
./obj_dir/VVexRiscv

2420
src/test/resources/hex/freeRTOS_demo.hex Normal file
View File

File diff suppressed because it is too large Load Diff

5
src/test/resources/hex/machineCsr.hex
View File

@ -15,7 +15,10 @@
:1000E000130000001300000013000000130E400076
:1000F000B712000093820280739042301300000018
:1001000013000000130000001300000013000000A3
:0C0110001300000013000000130E50004C
:100110001300000013000000130E5000B70110F090
:10012000938101F403A2010083A241001302F23F74
:1001300023A4410023A65100130E600013020008FF
:1001400073104230130E700073005010130E8000B5
:020000044000BA
:1000000013050000678000001305000067800000F2
:1000100097020000678082FF1305000067800000E0