Hardware/VexRiscv
1
0
Fork 0
mirror of https://github.com/SpinalHDL/VexRiscv.git synced 2025-01-03 03:43:39 -05:00
Code Issues Projects Releases Packages Wiki Activity

Fix CsrPlugin privilege crossing

Browse source
This commit is contained in:
Dolu1990 2020-10-28 12:57:20 +01:00
parent d490f903ea
commit 4209dc2792
1 changed files with 5 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
src/main/scala/vexriscv/plugin/CsrPlugin.scala
View file

@ -1136,7 +1136,11 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
}
}
illegalAccess setWhen(privilege < csrAddress(9 downto 8).asUInt)
when(privilege < csrAddress(9 downto 8).asUInt){
illegalAccess := True
readInstruction := False
writeInstruction := False
}
illegalAccess clearWhen(!arbitration.isValid || !input(IS_CSR))
}
}