Add fullNoMmuNoCache config

src/main/scala/VexRiscv/demo/GenFullNoMmuNoCache.scala

@@ -0,0 +1,64 @@
+package VexRiscv.demo
+
+import VexRiscv.Plugin._
+import VexRiscv.ip.{DataCacheConfig, InstructionCacheConfig}
+import VexRiscv.{Plugin, VexRiscv, VexRiscvConfig}
+import spinal.core._
+
+/**
+ * Created by spinalvm on 15.06.17.
+ */
+object GenFullNoMmuNoCache extends App{
+  def cpu() = new VexRiscv(
+    config = VexRiscvConfig(
+      plugins = List(
+        new PcManagerSimplePlugin(
+          resetVector = 0x00000000l,
+          fastPcCalculation = false
+        ),
+        new IBusSimplePlugin(
+          interfaceKeepData = false,
+          catchAccessFault = false
+        ),
+        new DBusSimplePlugin(
+          catchAddressMisaligned = false,
+          catchAccessFault = false
+        ),
+        new DecoderSimplePlugin(
+          catchIllegalInstruction = true
+        ),
+        new RegFilePlugin(
+          regFileReadyKind = Plugin.SYNC,
+          zeroBoot = true
+        ),
+        new IntAluPlugin,
+        new SrcPlugin(
+          separatedAddSub = false,
+          executeInsertion = true
+        ),
+        new FullBarrielShifterPlugin,
+        new HazardSimplePlugin(
+          bypassExecute           = true,
+          bypassMemory            = true,
+          bypassWriteBack         = true,
+          bypassWriteBackBuffer   = true,
+          pessimisticUseSrc       = false,
+          pessimisticWriteRegFile = false,
+          pessimisticAddressMatch = false
+        ),
+        new MulPlugin,
+        new DivPlugin,
+        new CsrPlugin(CsrPluginConfig.small),
+        new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))),
+        new BranchPlugin(
+          earlyBranch = false,
+          catchAddressMisaligned = true,
+          prediction = STATIC
+        ),
+        new YamlPlugin("cpu0.yaml")
+      )
+    )
+  )
+
+  SpinalVerilog(cpu())
+}

src/main/scala/VexRiscv/demo/SynthesisBench.scala

@@ -27,6 +27,13 @@ object SynthesisBench {
       SpinalVerilog(GenSmallAndProductive.cpu().setDefinitionName(getRtlPath().split("\\.").head))
     }
 
+    val fullNoMmuNoCache = new Rtl {
+      override def getName(): String = "VexRiscv full no MMU no cache"
+      override def getRtlPath(): String = "VexRiscvFullNoMmuNoCache.v"
+      SpinalVerilog(GenFullNoMmuNoCache.cpu().setDefinitionName(getRtlPath().split("\\.").head))
+    }
+
+
     val fullNoMmu = new Rtl {
       override def getName(): String = "VexRiscv full no MMU"
       override def getRtlPath(): String = "VexRiscvFullNoMmu.v"
@@ -39,7 +46,7 @@ object SynthesisBench {
       SpinalVerilog(GenFull.cpu().setDefinitionName(getRtlPath().split("\\.").head))
     }
 
-    val rtls = List(smallestNoCsr, smallest, smallAndProductive, fullNoMmu, full)
+    val rtls = List(smallestNoCsr, smallest, smallAndProductive, fullNoMmuNoCache, fullNoMmu, full)
 
     val targets = XilinxStdTargets(
       vivadoArtix7Path = "E:\\Xilinx\\Vivado\\2016.3\\bin"