update Synthesis results

README.md

@@ -66,53 +66,53 @@ The CPU configurations used below can be found in the `src/scala/vexriscv/demo`
 
 ```
 VexRiscv small (RV32I, 0.52 DMIPS/Mhz, no datapath bypass, no interrupt) ->
-    Artix 7     -> 253 Mhz 498 LUT 505 FF 
+    Artix 7     -> 243 Mhz 504 LUT 505 FF 
-    Cyclone V   -> 205 Mhz 350 ALMs
+    Cyclone V   -> 174 Mhz 352 ALMs
-    Cyclone IV  -> 172 Mhz 731 LUT 494 FF 
+    Cyclone IV  -> 179 Mhz 731 LUT 494 FF 
     iCE40       -> 92 Mhz 1130 LC
 
 VexRiscv small (RV32I, 0.52 DMIPS/Mhz, no datapath bypass) ->
-    Artix 7     -> 225 Mhz 549 LUT 563 FF 
+    Artix 7     -> 240 Mhz 556 LUT 566 FF 
-    Cyclone V   -> 194 Mhz 392 ALMs
+    Cyclone V   -> 194 Mhz 394 ALMs
-    Cyclone IV  -> 172 Mhz 830 LUT 551 FF 
+    Cyclone IV  -> 174 Mhz 831 LUT 555 FF 
     iCE40       -> 85 Mhz 1292 LC
 
 VexRiscv small and productive (RV32I, 0.82 DMIPS/Mhz)  ->
-    Artix 7     -> 213 Mhz 787 LUT 531 FF 
+    Artix 7     -> 232 Mhz 816 LUT 534 FF 
-    Cyclone V   -> 150 Mhz 487 ALMs
+    Cyclone V   -> 155 Mhz 492 ALMs
-    Cyclone IV  -> 151 Mhz 1,115 LUT 526 FF 
+    Cyclone IV  -> 155 Mhz 1,111 LUT 530 FF 
     iCE40       -> 63 Mhz 1596 LC
 
 VexRiscv small and productive with I$ (RV32I, 0.70 DMIPS/Mhz, 4KB-I$)  ->
-    Artix 7     -> 220 Mhz 719 LUT 570 FF 
+    Artix 7     -> 220 Mhz 730 LUT 570 FF 
-    Cyclone V   -> 147 Mhz 516 ALMs
+    Cyclone V   -> 142 Mhz 501 ALMs
-    Cyclone IV  -> 144 Mhz 1,139 LUT 532 FF 
+    Cyclone IV  -> 150 Mhz 1,139 LUT 536 FF 
     iCE40       -> 66 Mhz 1680 LC
 
 VexRiscv full no cache (RV32IM, 1.21 DMIPS/Mhz 2.30 Coremark/Mhz, single cycle barrel shifter, debug module, catch exceptions, static branch) ->
-    Artix 7     -> 210 Mhz 1410 LUT 975 FF 
+    Artix 7     -> 216 Mhz 1418 LUT 949 FF 
-    Cyclone V   -> 144 Mhz 927 ALMs
+    Cyclone V   -> 133 Mhz 933 ALMs
-    Cyclone IV  -> 141 Mhz 2,074 LUT 966 FF  
+    Cyclone IV  -> 143 Mhz 2,076 LUT 972 FF 
 
 VexRiscv full (RV32IM, 1.21 DMIPS/Mhz 2.30 Coremark/Mhz with cache trashing, 4KB-I$,4KB-D$, single cycle barrel shifter, debug module, catch exceptions, static branch) ->
-    Artix 7     -> 199 Mhz 1736 LUT 1120 FF 
+    Artix 7     -> 199 Mhz 1840 LUT 1158 FF 
-    Cyclone V   -> 137 Mhz 1,177 ALMs
+    Cyclone V   -> 141 Mhz 1,166 ALMs
-    Cyclone IV  -> 142 Mhz 2,409 LUT 1,061 FF 
+    Cyclone IV  -> 131 Mhz 2,407 LUT 1,067 FF 
 
 VexRiscv full max perf (HZ*IPC) -> (RV32IM, 1.38 DMIPS/Mhz 2.57 Coremark/Mhz, 8KB-I$,8KB-D$, single cycle barrel shifter, debug module, catch exceptions, dynamic branch prediction in the fetch stage, branch and shift operations done in the Execute stage) ->
-    Artix 7     -> 197 Mhz 1788 LUT 1210 FF 
+    Artix 7     -> 200 Mhz 1935 LUT 1216 FF 
-    Cyclone V   -> 130 Mhz 1,173 ALMs
+    Cyclone V   -> 130 Mhz 1,166 ALMs
-    Cyclone IV  -> 124 Mhz 2,483 LUT 1,114 FF 
+    Cyclone IV  -> 126 Mhz 2,484 LUT 1,120 FF 
 
 VexRiscv full with MMU (RV32IM, 1.24 DMIPS/Mhz 2.35 Coremark/Mhz, with cache trashing, 4KB-I$, 4KB-D$, single cycle barrel shifter, debug module, catch exceptions, dynamic branch, MMU) ->
-    Artix 7     -> 164 Mhz 2000 LUT 1501 FF 
+    Artix 7     -> 151 Mhz 2021 LUT 1541 FF 
-    Cyclone V   -> 125 Mhz 1,375 ALMs
+    Cyclone V   -> 124 Mhz 1,368 ALMs
-    Cyclone IV  -> 121 Mhz 2,821 LUT 1,444 FF 
+    Cyclone IV -> 128 Mhz 2,826 LUT 1,474 FF 
 
 VexRiscv linux balanced (RV32IMA, 1.21 DMIPS/Mhz 2.27 Coremark/Mhz, with cache trashing, 4KB-I$, 4KB-D$, single cycle barrel shifter, catch exceptions, static branch, MMU, Supervisor, Compatible with mainstream linux) ->
-    Artix 7     -> 176 Mhz 2678 LUT 2087 FF 
+    Artix 7     -> 180 Mhz 2883 LUT 2130 FF 
-    Cyclone V   -> 137 Mhz 1,797 ALMs
+    Cyclone V   -> 131 Mhz 1,764 ALMs
-    Cyclone IV  -> 120 Mhz 3,544 LUT 2,059 FF 
+    Cyclone IV  -> 121 Mhz 3,608 LUT 2,082 FF 
 ```
 
 The following configuration results in 1.44 DMIPS/MHz:
@@ -318,9 +318,9 @@ You can find some FPGA projects which instantiate the Briey SoC here (DE1-SoC, D
 Here are some measurements of Briey SoC timings and area :
 
 ```
-    Artix 7     -> 186 Mhz 3138 LUT 3328 FF
+Artix 7     -> 181 Mhz 3220 LUT 3181 FF 
-    Cyclone V   -> 139 Mhz 2,175 ALMs
+Cyclone V   -> 142 Mhz 2,222 ALMs
-    Cyclone IV  -> 129 Mhz 4,337 LUT 3,170 FF
+Cyclone IV  -> 130 Mhz 4,538 LUT 3,211 FF 
 ```
 
 ## Murax SoC
@@ -373,15 +373,15 @@ Here are some timing and area measurements of the Murax SoC:
 
 ```
 Murax interlocked stages (0.45 DMIPS/Mhz, 8 bits GPIO) ->
-  Artix 7    -> 215 Mhz 1044 LUT 1202 FF
+    Artix 7     -> 216 Mhz 1109 LUT 1201 FF 
-  Cyclone V  -> 173 Mhz 737 ALMs
+    Cyclone V   -> 182 Mhz 725 ALMs
-  Cyclone IV -> 144 Mhz 1,484 LUT 1,206 FF
+    Cyclone IV  -> 147 Mhz 1,551 LUT 1,223 FF 
     iCE40       ->  64 Mhz 2422 LC (nextpnr)
 
 MuraxFast bypassed stages (0.65 DMIPS/Mhz, 8 bits GPIO) ->
-  Artix 7    -> 229 Mhz 1269 LUT 1302 FF
+    Artix 7     -> 224 Mhz 1278 LUT 1300 FF 
-  Cyclone V  -> 159 Mhz 864 ALMs
+    Cyclone V   -> 173 Mhz 867 ALMs
-  Cyclone IV -> 137 Mhz 1,688 LUT 1,241 FF
+    Cyclone IV  -> 143 Mhz 1,755 LUT 1,258 FF 
     iCE40       ->  66 Mhz 2799 LC (nextpnr)
 ```
 

src/main/scala/vexriscv/demo/SynthesisBench.scala

@@ -117,7 +117,7 @@ object VexRiscvSynthesisBench {
     val targets = XilinxStdTargets() ++ AlteraStdTargets() ++  IcestormStdTargets().take(1)
 
     //    val targets = IcestormStdTargets()
-    Bench(rtls, targets, "/media/miaou/HD/linux/tmp/")
+    Bench(rtls, targets)
   }
 }
 
@@ -139,7 +139,7 @@ object BrieySynthesisBench {
 
     val targets = XilinxStdTargets() ++ AlteraStdTargets() ++ IcestormStdTargets().take(1)
 
-    Bench(rtls, targets, "/media/miaou/HD/linux/tmp")
+    Bench(rtls, targets)
   }
 }
 
@@ -173,7 +173,7 @@ object MuraxSynthesisBench {
 
     val targets = XilinxStdTargets() ++ AlteraStdTargets() ++  IcestormStdTargets().take(1)
 
-    Bench(rtls, targets, "/media/miaou/HD/linux/tmp")
+    Bench(rtls, targets)
   }
 }