ICache compressed is working
This commit is contained in:
Dolu1990
parent
76352b44fa
commit
4440047fb6
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@ -17,9 +17,12 @@ case class InstructionCacheConfig( cacheSize : Int,
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catchAccessFault : Boolean,
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catchMemoryTranslationMiss : Boolean,
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asyncTagMemory : Boolean,
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twoCycleCache : Boolean = false,
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twoCycleRam : Boolean = false,
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preResetFlush : Boolean = false){
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assert(!(twoCycleRam && !twoCycleCache))
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def dataOnDecode = twoCycleRam && wayCount > 1
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def burstSize = bytePerLine*8/memDataWidth
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def catchSomething = catchAccessFault || catchMemoryTranslationMiss || catchIllegalAccess
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@ -63,10 +66,12 @@ case class InstructionCacheCpuFetch(p : InstructionCacheConfig) extends Bundle w
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val pc = UInt(p.addressWidth bits)
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val data = Bits(p.cpuDataWidth bits)
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val mmuBus = MemoryTranslatorBus()
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val cacheMiss, error, mmuMiss, illegalAccess,isUser = ifGen(!p.twoCycleCache)(Bool)
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override def asMaster(): Unit = {
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out(isValid, isStuck, pc)
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inWithNull(data)
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inWithNull(error,mmuMiss,illegalAccess,data, cacheMiss)
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outWithNull(isUser)
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slaveWithNull(mmuBus)
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}
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}
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@ -74,19 +79,15 @@ case class InstructionCacheCpuFetch(p : InstructionCacheConfig) extends Bundle w
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case class InstructionCacheCpuDecode(p : InstructionCacheConfig) extends Bundle with IMasterSlave {
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val isValid = Bool
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val isUser = Bool
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val isStuck = Bool
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val pc = UInt(p.addressWidth bits)
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val cacheMiss = Bool
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val data = ifGen(p.dataOnDecode) (Bits(p.cpuDataWidth bits))
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val error = Bool
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val mmuMiss = Bool
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val illegalAccess = Bool
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val cacheMiss, error, mmuMiss, illegalAccess, isUser = ifGen(p.twoCycleCache)(Bool)
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override def asMaster(): Unit = {
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out(isValid, isUser, isStuck, pc)
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in(cacheMiss)
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inWithNull(error,mmuMiss,illegalAccess,data)
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out(isValid, isStuck, pc)
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outWithNull(isUser)
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inWithNull(error,mmuMiss,illegalAccess,data, cacheMiss)
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}
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}
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@ -94,9 +95,10 @@ case class InstructionCacheCpuBus(p : InstructionCacheConfig) extends Bundle wit
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val prefetch = InstructionCacheCpuPrefetch(p)
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val fetch = InstructionCacheCpuFetch(p)
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val decode = InstructionCacheCpuDecode(p)
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val fill = Flow(UInt(p.addressWidth bits))
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override def asMaster(): Unit = {
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master(prefetch, fetch, decode)
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master(prefetch, fetch, decode, fill)
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}
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}
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@ -218,6 +220,11 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
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val address = Reg(UInt(addressWidth bits))
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val hadError = RegInit(False) clearWhen(fire)
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when(io.cpu.fill.valid){
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valid := True
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address := io.cpu.fill.payload
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}
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io.cpu.prefetch.haltIt setWhen(valid)
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val flushCounter = Reg(UInt(log2Up(wayLineCount) + 1 bit)) init(if(preResetFlush) wayLineCount else 0)
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@ -311,10 +318,21 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
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io.cpu.fetch.mmuBus.cmd.isValid := io.cpu.fetch.isValid
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io.cpu.fetch.mmuBus.cmd.virtualAddress := io.cpu.fetch.pc
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io.cpu.fetch.mmuBus.cmd.bypassTranslation := False
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val resolution = ifGen(!twoCycleCache)( new Area{
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def stage[T <: Data](that : T) = RegNextWhen(that,!io.cpu.decode.isStuck)
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val mmuRsp = stage(io.cpu.fetch.mmuBus.rsp)
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io.cpu.fetch.cacheMiss := !hit.valid
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io.cpu.fetch.error := hit.error
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io.cpu.fetch.mmuMiss := mmuRsp.miss
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io.cpu.fetch.illegalAccess := !mmuRsp.allowExecute || (io.cpu.fetch.isUser && !mmuRsp.allowUser)
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})
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}
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val decodeStage = new Area{
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val decodeStage = ifGen(twoCycleCache) (new Area{
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def stage[T <: Data](that : T) = RegNextWhen(that,!io.cpu.decode.isStuck)
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val mmuRsp = stage(io.cpu.fetch.mmuBus.rsp)
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@ -335,16 +353,16 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
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}
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io.cpu.decode.cacheMiss := !hit.valid
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when( io.cpu.decode.isValid && io.cpu.decode.cacheMiss){
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io.cpu.prefetch.haltIt := True
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lineLoader.valid := True
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lineLoader.address := mmuRsp.physicalAddress //Could be optimise if mmu not used
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}
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// when( io.cpu.decode.isValid && io.cpu.decode.cacheMiss){
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// io.cpu.prefetch.haltIt := True
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// lineLoader.valid := True
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// lineLoader.address := mmuRsp.physicalAddress //Could be optimise if mmu not used
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// }
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// when(io.cpu)
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io.cpu.decode.error := hit.error
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io.cpu.decode.mmuMiss := mmuRsp.miss
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io.cpu.decode.illegalAccess := !mmuRsp.allowExecute || (io.cpu.decode.isUser && !mmuRsp.allowUser)
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}
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})
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}
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@ -44,12 +44,12 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
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}
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var decodeExceptionPort : Flow[ExceptionCause] = null
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// var decodeExceptionPort : Flow[ExceptionCause] = null
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override def setup(pipeline: VexRiscv): Unit = {
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fetcherHalt = False
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if(catchAccessFault || catchAddressMisaligned) {
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val exceptionService = pipeline.service(classOf[ExceptionService])
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decodeExceptionPort = exceptionService.newExceptionPort(pipeline.decode,1).setName("iBusErrorExceptionnPort")
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// decodeExceptionPort = exceptionService.newExceptionPort(pipeline.decode,1).setName("iBusErrorExceptionnPort")
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}
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pipeline(RVC_GEN) = compressedGen
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@ -200,8 +200,10 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
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// ...
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val readyForError = True
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val outputBeforeStage = Stream(FetchRsp())
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val output = if(rspStageGen) outputBeforeStage.m2sPipeWithFlush(flush) else outputBeforeStage
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if(rspStageGen) readyForError.clearWhen(output.valid)
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}
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val decompressor = ifGen(decodePcGen)(new Area{
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@ -209,7 +211,6 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
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val output = Stream(FetchRsp())
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val bufferValid = RegInit(False)
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val bufferError = Reg(Bool)
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val bufferData = Reg(Bits(16 bits))
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val raw = Mux(
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@ -219,11 +220,10 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
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)
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val isRvc = raw(1 downto 0) =/= 3
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val decompressed = RvcDecompressor(raw(15 downto 0))
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output.valid := isRvc ? (bufferValid || input.valid) | (input.valid && (bufferValid || !input.pc(1)))
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output.valid := (isRvc ? (bufferValid || input.valid) | (input.valid && (bufferValid || !input.pc(1))))
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output.pc := input.pc
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output.isRvc := isRvc
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output.rsp.inst := isRvc ? decompressed | raw
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output.rsp.error := (bufferValid && bufferError) || (input.valid && input.rsp.error && (!isRvc || (isRvc && !bufferValid)))
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input.ready := (bufferValid ? (!isRvc && output.ready) | (input.pc(1) || output.ready))
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@ -231,19 +231,21 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
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when(input.ready){
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when(input.valid) {
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bufferValid := !(!isRvc && !input.pc(1) && !bufferValid) && !(isRvc && input.pc(1))
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bufferError := input.rsp.error
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bufferData := input.rsp.inst(31 downto 16)
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}
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}
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bufferValid.clearWhen(flush)
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iBusRsp.readyForError.clearWhen(bufferValid && isRvc)
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})
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def condApply[T](that : T, cond : Boolean)(func : (T) => T) = if(cond)func(that) else that
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val injector = new Area {
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val inputBeforeHalt = condApply(if(decodePcGen) decompressor.output else iBusRsp.output, injectorReadyCutGen)(_.s2mPipe(flush))
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if(injectorReadyCutGen) iBusRsp.readyForError.clearWhen(inputBeforeHalt.valid)
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val decodeInput = if(injectorStage){
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val decodeInput = inputBeforeHalt.m2sPipeWithFlush(killLastStage)
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decode.insert(INSTRUCTION_ANTICIPATED) := Mux(decode.arbitration.isStuck, decode.input(INSTRUCTION), inputBeforeHalt.rsp.inst)
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iBusRsp.readyForError.clearWhen(decodeInput.valid)
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decodeInput
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} else {
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inputBeforeHalt
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@ -273,11 +275,11 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
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decode.insert(INSTRUCTION_READY) := True
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if(compressedGen) decode.insert(IS_RVC) := decodeInput.isRvc
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if(catchAccessFault){
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decodeExceptionPort.valid := decode.arbitration.isValid && decodeInput.rsp.error
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decodeExceptionPort.code := 1
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decodeExceptionPort.badAddr := decode.input(PC)
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}
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// if(catchAccessFault){
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// decodeExceptionPort.valid := decode.arbitration.isValid && decodeInput.rsp.error
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// decodeExceptionPort.code := 1
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// decodeExceptionPort.badAddr := decode.input(PC)
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// }
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}
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prediction match {
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@ -50,10 +50,10 @@ class IBusCachedPlugin(config : InstructionCacheConfig, memoryTranslatorPortConf
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redoBranch = pipeline.service(classOf[JumpService]).createJumpInterface(pipeline.decode, priority = 1) //Priority 1 will win against branch predictor
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if(catchSomething) {
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val exceptionService = pipeline.service(classOf[ExceptionService])
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decodeExceptionPort = exceptionService.newExceptionPort(pipeline.decode,1)
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}
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// if(catchSomething) {
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// val exceptionService = pipeline.service(classOf[ExceptionService])
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// decodeExceptionPort = exceptionService.newExceptionPort(pipeline.decode,1)
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// }
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// if(pipeline.serviceExist(classOf[MemoryTranslator]))
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// ??? //TODO
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@ -114,43 +114,52 @@ class IBusCachedPlugin(config : InstructionCacheConfig, memoryTranslatorPortConf
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cache.io.cpu.fetch.mmuBus.rsp.miss := False
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}
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if (dataOnDecode) {
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decode.insert(INSTRUCTION) := cache.io.cpu.decode.data
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} else {
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iBusRsp.outputBeforeStage.arbitrationFrom(iBusRsp.inputPipeline(0))
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val missHalt = cache.io.cpu.fetch.isValid && cache.io.cpu.fetch.cacheMiss
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iBusRsp.outputBeforeStage.arbitrationFrom(iBusRsp.inputPipeline(0).haltWhen(missHalt))
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iBusRsp.outputBeforeStage.rsp.inst := cache.io.cpu.fetch.data
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iBusRsp.outputBeforeStage.pc := iBusRsp.inputPipeline(0).payload
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}
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cache.io.cpu.decode.pc := injector.inputBeforeHalt.pc
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val ownDecode = pipeline.plugins.filter(_.isInstanceOf[InstructionInjector]).foldLeft(True)(_ && !_.asInstanceOf[InstructionInjector].isInjecting(decode))
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cache.io.cpu.decode.isValid := decode.arbitration.isValid && ownDecode
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cache.io.cpu.decode.isStuck := !injector.inputBeforeHalt.ready
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cache.io.cpu.decode.isUser := (if (privilegeService != null) privilegeService.isUser(decode) else False)
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// cache.io.cpu.decode.pc := decode.input(PC)
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redoBranch.valid := decode.arbitration.isValid && ownDecode && cache.io.cpu.decode.cacheMiss && !cache.io.cpu.decode.mmuMiss && !cache.io.cpu.decode.illegalAccess
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cache.io.cpu.fill.valid := missHalt && iBusRsp.readyForError
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cache.io.cpu.fill.payload := cache.io.cpu.fetch.pc
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redoBranch.valid := (RegNext(cache.io.cpu.fill.valid && !flush) init(False))
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redoBranch.payload := decode.input(PC)
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when(redoBranch.valid) {
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decode.arbitration.redoIt := True
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decode.arbitration.flushAll := True
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}
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// if (dataOnDecode) {
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// decode.insert(INSTRUCTION) := cache.io.cpu.decode.data
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// } else {
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// iBusRsp.outputBeforeStage.arbitrationFrom(iBusRsp.inputPipeline(0))
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// iBusRsp.outputBeforeStage.rsp.inst := cache.io.cpu.fetch.data
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// iBusRsp.outputBeforeStage.pc := iBusRsp.inputPipeline(0).payload
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// }
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//
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// cache.io.cpu.decode.pc := injector.inputBeforeHalt.pc
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//
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// val ownDecode = pipeline.plugins.filter(_.isInstanceOf[InstructionInjector]).foldLeft(True)(_ && !_.asInstanceOf[InstructionInjector].isInjecting(decode))
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// cache.io.cpu.decode.isValid := decode.arbitration.isValid && ownDecode
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// cache.io.cpu.decode.isStuck := !injector.inputBeforeHalt.ready
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// cache.io.cpu.decode.isUser := (if (privilegeService != null) privilegeService.isUser(decode) else False)
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// // cache.io.cpu.decode.pc := decode.input(PC)
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//
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// redoBranch.valid := decode.arbitration.isValid && ownDecode && cache.io.cpu.decode.cacheMiss && !cache.io.cpu.decode.mmuMiss && !cache.io.cpu.decode.illegalAccess
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// redoBranch.payload := decode.input(PC)
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// when(redoBranch.valid) {
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// decode.arbitration.redoIt := True
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// decode.arbitration.flushAll := True
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// }
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// val redo = RegInit(False) clearWhen(decode.arbitration.isValid) setWhen(redoBranch.valid)
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// when(redoBranch.valid || redo){
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// service(classOf[InterruptionInhibitor]).inhibateInterrupts()
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// }
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if (catchSomething) {
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val accessFault = if (catchAccessFault) cache.io.cpu.decode.error else False
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val mmuMiss = if (catchMemoryTranslationMiss) cache.io.cpu.decode.mmuMiss else False
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val illegalAccess = if (catchIllegalAccess) cache.io.cpu.decode.illegalAccess else False
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// if (catchSomething) {
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// val accessFault = if (catchAccessFault) cache.io.cpu.decode.error else False
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// val mmuMiss = if (catchMemoryTranslationMiss) cache.io.cpu.decode.mmuMiss else False
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// val illegalAccess = if (catchIllegalAccess) cache.io.cpu.decode.illegalAccess else False
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decodeExceptionPort.valid := decode.arbitration.isValid && ownDecode && (accessFault || mmuMiss || illegalAccess)
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decodeExceptionPort.code := mmuMiss ? U(14) | 1
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decodeExceptionPort.badAddr := decode.input(PC)
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}
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// decodeExceptionPort.valid := decode.arbitration.isValid && ownDecode && (accessFault || mmuMiss || illegalAccess)
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// decodeExceptionPort.code := mmuMiss ? U(14) | 1
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// decodeExceptionPort.badAddr := decode.input(PC)
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// }
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memory plug new Area {
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