mirror of
https://github.com/SpinalHDL/VexRiscv.git
synced 2025-01-03 03:43:39 -05:00
fpu merged i2f with load pipeline
This commit is contained in:
Dolu1990
parent
3334364f5f
commit
444bcdba0a
4 changed files with 146 additions and 135 deletions
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@ -47,6 +47,8 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val source = Source()
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val rd = p.rfAddress()
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val lockId = lockIdType()
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val i2f = Bool()
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val arg = Bits(2 bits)
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}
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case class ShortPipInput() extends Bundle{
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@ -228,13 +230,14 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val input = read.output.combStage()
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input.ready := False
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val loadHit = List(FpuOpcode.LOAD, FpuOpcode.FMV_W_X).map(input.opcode === _).orR
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val loadHit = List(FpuOpcode.LOAD, FpuOpcode.FMV_W_X, FpuOpcode.I2F).map(input.opcode === _).orR
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val load = Stream(LoadInput())
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load.valid := input.valid && loadHit
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input.ready setWhen(loadHit && load.ready)
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load.payload.assignSomeByName(read.output.payload)
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load.i2f := input.opcode === FpuOpcode.I2F
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val shortPipHit = List(FpuOpcode.STORE, FpuOpcode.F2I, FpuOpcode.CMP, FpuOpcode.I2F, FpuOpcode.MIN_MAX, FpuOpcode.SGNJ, FpuOpcode.FMV_X_W, FpuOpcode.FCLASS).map(input.opcode === _).orR
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val shortPipHit = List(FpuOpcode.STORE, FpuOpcode.F2I, FpuOpcode.CMP, FpuOpcode.MIN_MAX, FpuOpcode.SGNJ, FpuOpcode.FMV_X_W, FpuOpcode.FCLASS).map(input.opcode === _).orR
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val shortPip = Stream(ShortPipInput())
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input.ready setWhen(shortPipHit && shortPip.ready)
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shortPip.valid := input.valid && shortPipHit
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@ -289,7 +292,9 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val source = Source()
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val lockId = lockIdType()
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val rd = p.rfAddress()
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val value = FpuFloat(exponentSize = p.internalExponentSize-1, mantissaSize = p.internalMantissaSize)
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val value = p.storeLoadType()
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val i2f = Bool()
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val arg = Bits(2 bits)
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}
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val s0 = new Area{
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@ -304,18 +309,28 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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output.source := input.source
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output.lockId := input.lockId
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output.rd := input.rd
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output.value.mantissa := feed.value(0, 23 bits).asUInt
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output.value.exponent := feed.value(23, 8 bits).asUInt
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output.value.sign := feed.value(31)
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output.value := feed.value
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output.i2f := input.i2f
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output.arg := input.arg
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}
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// val i2fSign = input.arg(0) && input.value.msb
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// val i2fUnsigned = input.value.asUInt.twoComplement(i2fSign).resize(32 bits)
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// val i2fLog2 = OHToUInt(OHMasking.last(i2fUnsigned))
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// val i2fShifted = (i2fUnsigned << p.internalMantissaSize) >> i2fLog2
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// rfOutput.value.sign := i2fSign
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// rfOutput.value.exponent := i2fLog2 +^ exponentOne
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// rfOutput.value.mantissa := U(i2fShifted).resized
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// rfOutput.value.special := False //TODO
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val s1 = new Area{
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val input = s0.output.stage()
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val busy = False
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val f32Mantissa = input.value.mantissa
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val f32Exponent = input.value.exponent
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val f32Sign = input.value.sign
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val f32Mantissa = input.value(0, 23 bits).asUInt
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val f32Exponent = input.value(23, 8 bits).asUInt
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val f32Sign = input.value(31)
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val expZero = f32Exponent === 0
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val expOne = f32Exponent === 255
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@ -329,18 +344,31 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val isNan = expOne && !manZero
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val isQuiet = f32Mantissa.msb
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val subnormal = new Area{
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val fsm = new Area{
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val manTop = Reg(UInt(log2Up(p.internalMantissaSize) bits))
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val shift = isSubnormal ? manTop | U(0)
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val shift = CombInit(manTop)
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val counter = Reg(UInt(log2Up(p.internalMantissaSize+1) bits))
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val done, boot = Reg(Bool())
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when(isSubnormal && !done){
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val done, boot, patched = Reg(Bool())
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val ohInput = CombInit(input.value(0, 32 max p.internalMantissaSize bits))
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when(!input.i2f) { ohInput(9, 23 bits) := input.value(0, 23 bits) }
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val i2fZero = Reg(Bool)
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when(input.valid && (input.i2f || isSubnormal) && !done){
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busy := True
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when(boot){
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manTop := OHToUInt(OHMasking.first((f32Mantissa).reversed))
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boot := False
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when(input.i2f && !patched && input.value.msb && input.arg(0)){
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input.value.getDrivingReg(0, 32 bits) := B(input.value.asUInt.twoComplement(True).resize(32 bits))
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patched := True
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} otherwise {
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manTop := OHToUInt(OHMasking.first((ohInput).reversed))
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boot := False
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i2fZero := input.value(31 downto 0) === 0
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}
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} otherwise {
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input.value.mantissa.getDrivingReg := input.value.mantissa |<< 1
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when(input.i2f){
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input.value.getDrivingReg(0, 32 bits) := input.value(0, 32 bits) |<< 1
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} otherwise {
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input.value.getDrivingReg(0, 23 bits) := input.value(0, 23 bits) |<< 1
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}
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counter := counter + 1
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when(counter === shift) {
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done := True
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@ -358,16 +386,20 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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counter := 0
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done := False
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boot := True
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patched := False
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}
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}
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val i2fSign = fsm.patched
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val i2fShifted = input.value.takeHigh(23)
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val recoded = p.internalFloating()
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recoded.mantissa := f32Mantissa
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recoded.exponent := (f32Exponent -^ subnormal.expOffset + (exponentOne - 127)).resized
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recoded.exponent := (f32Exponent -^ fsm.expOffset + (exponentOne - 127)).resized
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recoded.sign := f32Sign
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recoded.setNormal
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when(isZero){recoded.setZero}
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//when(isSubnormal){recoded.setSubnormal}
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when(isInfinity){recoded.setInfinity}
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when(isNan){recoded.setNan}
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@ -376,6 +408,13 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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output.lockId := input.lockId
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output.rd := input.rd
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output.value := recoded
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when(input.i2f){
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output.value.sign := i2fSign
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output.value.exponent := (U(exponentOne+31) - fsm.manTop).resized
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output.value.mantissa := U(i2fShifted)
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output.value.setNormal
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when(fsm.i2fZero) { output.value.setZero }
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}
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}
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}
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@ -401,10 +440,9 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val subnormal = new Area{
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val needRecoding = List(FpuOpcode.FMV_X_W, FpuOpcode.STORE).map(_ === input.opcode).orR
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val manTop = Reg(UInt(log2Up(p.internalMantissaSize) bits))
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val shift = isSubnormal ? manTop | U(0)
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val counter = Reg(UInt(log2Up(p.internalMantissaSize+1) bits))
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val done, boot = Reg(Bool())
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when(needRecoding && isSubnormal && !done){
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when(input.valid && needRecoding && isSubnormal && !done){
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halt := True
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when(boot){
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manTop := (U(exponentOne - 127) - recoded.exponent).resized
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@ -412,7 +450,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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} otherwise {
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recoded.mantissa.getDrivingReg := (U(counter === 0) @@ recoded.mantissa) >> 1
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counter := counter + 1
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when(counter === shift) {
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when(counter === manTop) {
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done := True
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}
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}
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@ -450,11 +488,6 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val f2iUnsigned = f2iShifted >> p.internalMantissaSize
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val f2iResult = (f2iUnsigned.twoComplement(input.arg(0) && input.rs1.sign)).asBits.resize(32 bits)
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val i2fSign = input.arg(0) && input.value.msb
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val i2fUnsigned = input.value.asUInt.twoComplement(i2fSign).resize(32 bits)
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val i2fLog2 = OHToUInt(OHMasking.last(i2fUnsigned))
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val i2fShifted = (i2fUnsigned << p.internalMantissaSize) >> i2fLog2
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val bothZero = input.rs1.isZero && input.rs2.isZero
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val rs1Equal = input.rs1 === input.rs2
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val rs1AbsSmaller = (input.rs1.exponent @@ input.rs1.mantissa) < (input.rs2.exponent @@ input.rs2.mantissa)
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@ -496,7 +529,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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is(FpuOpcode.FCLASS) { result := fclassResult.resized }
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}
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val toFpuRf = List(FpuOpcode.MIN_MAX, FpuOpcode.I2F, FpuOpcode.SGNJ).map(input.opcode === _).orR
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val toFpuRf = List(FpuOpcode.MIN_MAX, FpuOpcode.SGNJ).map(input.opcode === _).orR
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rfOutput.valid := input.valid && toFpuRf && !halt
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rfOutput.source := input.source
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@ -504,12 +537,6 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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rfOutput.rd := input.rd
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rfOutput.value.assignDontCare()
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switch(input.opcode){
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is(FpuOpcode.I2F){
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rfOutput.value.sign := i2fSign
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rfOutput.value.exponent := i2fLog2 +^ exponentOne
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rfOutput.value.mantissa := U(i2fShifted).resized
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rfOutput.value.special := False //TODO
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}
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is(FpuOpcode.MIN_MAX){
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rfOutput.value := minMaxResult
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}
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@ -550,7 +577,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val exp = math.exp + U(needShift)
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val man = needShift ? mulRounded(1, p.internalMantissaSize bits) | mulRounded(0, p.internalMantissaSize bits)
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val forceZero = input.rs1.isZeroOrSubnormal || input.rs2.isZeroOrSubnormal
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val forceZero = input.rs1.isZero || input.rs2.isZero
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val forceUnderflow = exp <= exponentOne + exponentOne - 127 - 23 // 0x6A //TODO
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val forceOverflow = exp > exponentOne + exponentOne + 127 || input.rs1.isInfinity || input.rs2.isInfinity
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val forceNan = input.rs1.isNan || input.rs2.isNan || ((input.rs1.isInfinity || input.rs2.isInfinity) && (input.rs1.isZero || input.rs2.isZero))
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@ -717,8 +744,8 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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decode.divSqrtToMul.rs2.exponent := divExp.value + iterationValue.msb.asUInt
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decode.divSqrtToMul.rs2.mantissa := (iterationValue << 1).resized
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val zero = input.rs2.isInfinity
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val overflow = input.rs2.isZeroOrSubnormal
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val nan = input.rs2.isNan || (input.rs1.isZeroOrSubnormal && input.rs2.isZeroOrSubnormal)
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val overflow = input.rs2.isZero
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val nan = input.rs2.isNan || (input.rs1.isZero && input.rs2.isZero)
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when(nan){
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decode.divSqrtToMul.rs2.setNanQuiet
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@ -785,12 +812,12 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val shifter = new Area {
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val exp21 = input.rs2.exponent -^ input.rs1.exponent
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val rs1ExponentBigger = (exp21.msb || input.rs2.isZeroOrSubnormal) && !input.rs1.isZeroOrSubnormal
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val rs1ExponentBigger = (exp21.msb || input.rs2.isZero) && !input.rs1.isZero
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val rs1ExponentEqual = input.rs1.exponent === input.rs2.exponent
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val rs1MantissaBigger = input.rs1.mantissa > input.rs2.mantissa
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val absRs1Bigger = ((rs1ExponentBigger || rs1ExponentEqual && rs1MantissaBigger) && !input.rs1.isZeroOrSubnormal || input.rs1.isInfinity) && !input.rs2.isInfinity
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val absRs1Bigger = ((rs1ExponentBigger || rs1ExponentEqual && rs1MantissaBigger) && !input.rs1.isZero || input.rs1.isInfinity) && !input.rs2.isInfinity
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val shiftBy = rs1ExponentBigger ? (0-exp21) | exp21
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val passThrough = shiftBy >= p.internalMantissaSize || (input.rs1.isZeroOrSubnormal) || (input.rs2.isZeroOrSubnormal)
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val passThrough = shiftBy >= p.internalMantissaSize || (input.rs1.isZero) || (input.rs2.isZero)
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//Note that rs1ExponentBigger can be replaced by absRs1Bigger bellow to avoid xsigned two complement in math block at expense of combinatorial path
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val xySign = absRs1Bigger ? input.rs1.sign | input.rs2.sign
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@ -827,8 +854,8 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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// val mantissaShifted = (xyMantissa |<< shift)
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// val mantissa = ((xyMantissa ) >> 2) + U(xyMantissa(1))
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val exponent = xyExponent -^ shift + 1
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xySign clearWhen(input.rs1.isZeroOrSubnormal && input.rs2.isZeroOrSubnormal)
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val forceZero = xyMantissa === 0 || exponent.msb || (input.rs1.isZeroOrSubnormal && input.rs2.isZeroOrSubnormal)
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xySign clearWhen(input.rs1.isZero && input.rs2.isZero)
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val forceZero = xyMantissa === 0 || exponent.msb || (input.rs1.isZero && input.rs2.isZero)
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val forceOverflow = exponent === exponentOne + 128 || (input.rs1.isInfinity || input.rs2.isInfinity)
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val forceNan = input.rs1.isNan || input.rs2.isNan || (input.rs1.isInfinity && input.rs2.isInfinity && (input.rs1.sign ^ input.rs2.sign))
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}
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@ -847,7 +874,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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output.value.setNanQuiet
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} elsewhen(norm.forceZero) {
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output.value.setZero
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when(norm.xyMantissa === 0 || input.rs1.isZeroOrSubnormal && input.rs2.isZeroOrSubnormal){
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when(norm.xyMantissa === 0 || input.rs1.isZero && input.rs2.isZero){
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output.value.sign := input.rs1.sign && input.rs2.sign
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}
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} elsewhen(norm.forceOverflow) {
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@ -856,26 +883,6 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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}
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// val format = new Area{
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// val input = pipeArbiter.arbitrated.combStage()
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//
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// val rotate = new Area{
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// val input = Bits(p.internalMantissaSize bits)
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// val shift = UInt(log2Up(p.internalMantissaSize) bits)
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// val output = input.rotateLeft(shift)
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// }
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//
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// val decode = new Area{
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// val sign = input.raw(31)
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// val exp = input.raw(23, 8 bits).asUInt
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// val man = input.raw(23, 8 bits).asUInt
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// val isSubnormal = exp === 0 //zero ?
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// val manTop = OHToUInt(OHMasking.first((man ## U"1").reversed))
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// val shift = isSubnormal ? manTop | U(0)
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// rotate.shift := shift
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// }
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// }
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val write = new Area{
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val arbitrated = StreamArbiterFactory.lowerFirst.noLock.on(List(load.s1.output, add.output, mul.output, shortPip.rfOutput))
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val isCommited = rf.lock.map(_.commited).read(arbitrated.lockId)
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@ -25,9 +25,8 @@ case class FpuFloatDecoded() extends Bundle{
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object FpuFloat{
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val ZERO = 0
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val SUBNORMAL = 1
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val INFINITY = 2
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val NAN = 3
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val INFINITY = 1
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val NAN = 2
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}
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case class FpuFloat(exponentSize: Int,
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@ -45,22 +44,17 @@ case class FpuFloat(exponentSize: Int,
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ret
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}
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def isZeroOrSubnormal = special && exponent(1) === False
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def isNormal = !special
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def isZero = special && exponent(1 downto 0) === 0
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//def isSubnormal = special && exponent(1 downto 0) === 1
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def isInfinity = special && exponent(1 downto 0) === 2
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def isNan = special && exponent(1 downto 0) === 3
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def isZero = special && exponent(1 downto 0) === FpuFloat.ZERO
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def isInfinity = special && exponent(1 downto 0) === FpuFloat.INFINITY
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def isNan = special && exponent(1 downto 0) === FpuFloat.NAN
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def isQuiet = mantissa.msb
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def setNormal = { special := False }
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def setZero = { special := True; exponent(1 downto 0) := 0 }
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//def setSubnormal = { special := True; exponent(1 downto 0) := 1 }
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def setInfinity = { special := True; exponent(1 downto 0) := 2 }
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def setNan = { special := True; exponent(1 downto 0) := 3 }
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def setNanQuiet = { special := True; exponent(1 downto 0) := 3; mantissa.msb := True }
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def setZero = { special := True; exponent(1 downto 0) := FpuFloat.ZERO }
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def setInfinity = { special := True; exponent(1 downto 0) := FpuFloat.INFINITY }
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def setNan = { special := True; exponent(1 downto 0) := FpuFloat.NAN }
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def setNanQuiet = { special := True; exponent(1 downto 0) := FpuFloat.NAN ; mantissa.msb := True }
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def decode() = {
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val ret = FpuFloatDecoded()
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@ -122,7 +116,6 @@ case class FpuCompletion() extends Bundle{
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case class FpuCmd(p : FpuParameter) extends Bundle{
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val opcode = p.Opcode()
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val value = Bits(32 bits) // Int to float
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val arg = Bits(2 bits)
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val rs1, rs2, rs3 = p.rfAddress()
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val rd = p.rfAddress()
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@ -161,15 +161,13 @@ class FpuPlugin(externalFpu : Boolean = false,
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//Maybe it might be better to not fork before fire to avoid RF stall on commits
|
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val forked = Reg(Bool) setWhen(port.cmd.fire) clearWhen(!arbitration.isStuck) init(False)
|
||||
|
||||
val intRfReady = Reg(Bool()) setWhen(!arbitration.isStuckByOthers) clearWhen(!arbitration.isStuck) //TODO is that still in use ?
|
||||
val hazard = (input(RS1_USE) && !intRfReady) || csr.pendings.msb || csr.csrActive
|
||||
val hazard = csr.pendings.msb || csr.csrActive
|
||||
|
||||
arbitration.haltItself setWhen(arbitration.isValid && input(FPU_ENABLE) && hazard)
|
||||
arbitration.haltItself setWhen(port.cmd.isStall)
|
||||
|
||||
port.cmd.valid := arbitration.isValid && input(FPU_ENABLE) && !forked && !hazard
|
||||
port.cmd.opcode := input(FPU_OPCODE)
|
||||
port.cmd.value := RegNext(output(RS1))
|
||||
port.cmd.arg := input(FPU_ARG)
|
||||
port.cmd.rs1 := ((input(FPU_OPCODE) === FpuOpcode.STORE) ? input(INSTRUCTION)(rs2Range).asUInt | input(INSTRUCTION)(rs1Range).asUInt)
|
||||
port.cmd.rs2 := input(INSTRUCTION)(rs2Range).asUInt
|
||||
|
|
@ -179,7 +177,7 @@ class FpuPlugin(externalFpu : Boolean = false,
|
|||
|
||||
insert(FPU_FORKED) := forked || port.cmd.fire
|
||||
|
||||
insert(FPU_COMMIT_SYNC) := List(FpuOpcode.LOAD, FpuOpcode.FMV_W_X).map(_ === input(FPU_OPCODE)).orR
|
||||
insert(FPU_COMMIT_SYNC) := List(FpuOpcode.LOAD, FpuOpcode.FMV_W_X, FpuOpcode.I2F).map(_ === input(FPU_OPCODE)).orR
|
||||
insert(FPU_COMMIT_LOAD) := input(FPU_OPCODE) === FpuOpcode.LOAD
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -64,7 +64,6 @@ class FpuTest extends FunSuite{
|
|||
def loadRaw(rd : Int, value : BigInt): Unit ={
|
||||
cmdQueue += {cmd =>
|
||||
cmd.opcode #= cmd.opcode.spinalEnum.LOAD
|
||||
cmd.value.randomize()
|
||||
cmd.rs1.randomize()
|
||||
cmd.rs2.randomize()
|
||||
cmd.rs3.randomize()
|
||||
|
|
@ -85,7 +84,6 @@ class FpuTest extends FunSuite{
|
|||
def storeRaw(rs : Int)(body : FpuRsp => Unit): Unit ={
|
||||
cmdQueue += {cmd =>
|
||||
cmd.opcode #= cmd.opcode.spinalEnum.STORE
|
||||
cmd.value.randomize()
|
||||
cmd.rs1 #= rs
|
||||
cmd.rs2.randomize()
|
||||
cmd.rs3.randomize()
|
||||
|
|
@ -103,7 +101,6 @@ class FpuTest extends FunSuite{
|
|||
def mul(rd : Int, rs1 : Int, rs2 : Int): Unit ={
|
||||
cmdQueue += {cmd =>
|
||||
cmd.opcode #= cmd.opcode.spinalEnum.MUL
|
||||
cmd.value.randomize()
|
||||
cmd.rs1 #= rs1
|
||||
cmd.rs2 #= rs2
|
||||
cmd.rs3.randomize()
|
||||
|
|
@ -119,7 +116,6 @@ class FpuTest extends FunSuite{
|
|||
def add(rd : Int, rs1 : Int, rs2 : Int): Unit ={
|
||||
cmdQueue += {cmd =>
|
||||
cmd.opcode #= cmd.opcode.spinalEnum.ADD
|
||||
cmd.value.randomize()
|
||||
cmd.rs1 #= rs1
|
||||
cmd.rs2 #= rs2
|
||||
cmd.rs3.randomize()
|
||||
|
|
@ -135,7 +131,6 @@ class FpuTest extends FunSuite{
|
|||
def div(rd : Int, rs1 : Int, rs2 : Int): Unit ={
|
||||
cmdQueue += {cmd =>
|
||||
cmd.opcode #= cmd.opcode.spinalEnum.DIV
|
||||
cmd.value.randomize()
|
||||
cmd.rs1 #= rs1
|
||||
cmd.rs2 #= rs2
|
||||
cmd.rs3.randomize()
|
||||
|
|
@ -151,7 +146,6 @@ class FpuTest extends FunSuite{
|
|||
def sqrt(rd : Int, rs1 : Int): Unit ={
|
||||
cmdQueue += {cmd =>
|
||||
cmd.opcode #= cmd.opcode.spinalEnum.SQRT
|
||||
cmd.value.randomize()
|
||||
cmd.rs1 #= rs1
|
||||
cmd.rs2.randomize()
|
||||
cmd.rs3.randomize()
|
||||
|
|
@ -167,7 +161,6 @@ class FpuTest extends FunSuite{
|
|||
def fma(rd : Int, rs1 : Int, rs2 : Int, rs3 : Int): Unit ={
|
||||
cmdQueue += {cmd =>
|
||||
cmd.opcode #= cmd.opcode.spinalEnum.FMA
|
||||
cmd.value.randomize()
|
||||
cmd.rs1 #= rs1
|
||||
cmd.rs2 #= rs2
|
||||
cmd.rs3 #= rs3
|
||||
|
|
@ -184,7 +177,6 @@ class FpuTest extends FunSuite{
|
|||
def cmp(rs1 : Int, rs2 : Int)(body : FpuRsp => Unit): Unit ={
|
||||
cmdQueue += {cmd =>
|
||||
cmd.opcode #= cmd.opcode.spinalEnum.CMP
|
||||
cmd.value.randomize()
|
||||
cmd.rs1 #= rs1
|
||||
cmd.rs2 #= rs2
|
||||
cmd.rs3.randomize()
|
||||
|
|
@ -197,7 +189,6 @@ class FpuTest extends FunSuite{
|
|||
def f2i(rs1 : Int, signed : Boolean)(body : FpuRsp => Unit): Unit ={
|
||||
cmdQueue += {cmd =>
|
||||
cmd.opcode #= cmd.opcode.spinalEnum.F2I
|
||||
cmd.value.randomize()
|
||||
cmd.rs1 #= rs1
|
||||
cmd.rs2.randomize()
|
||||
cmd.rs3.randomize()
|
||||
|
|
@ -210,7 +201,6 @@ class FpuTest extends FunSuite{
|
|||
def i2f(rd : Int, value : Int, signed : Boolean): Unit ={
|
||||
cmdQueue += {cmd =>
|
||||
cmd.opcode #= cmd.opcode.spinalEnum.I2F
|
||||
cmd.value #= value.toLong & 0xFFFFFFFFl
|
||||
cmd.rs1.randomize()
|
||||
cmd.rs2.randomize()
|
||||
cmd.rs3.randomize()
|
||||
|
|
@ -219,14 +209,14 @@ class FpuTest extends FunSuite{
|
|||
}
|
||||
commitQueue += {cmd =>
|
||||
cmd.write #= true
|
||||
cmd.sync #= false
|
||||
cmd.sync #= true
|
||||
cmd.value #= value.toLong & 0xFFFFFFFFl
|
||||
}
|
||||
}
|
||||
|
||||
def fmv_x_w(rs1 : Int)(body : FpuRsp => Unit): Unit ={
|
||||
cmdQueue += {cmd =>
|
||||
cmd.opcode #= cmd.opcode.spinalEnum.FMV_X_W
|
||||
cmd.value.randomize()
|
||||
cmd.rs1 #= rs1
|
||||
cmd.rs2.randomize()
|
||||
cmd.rs3.randomize()
|
||||
|
|
@ -239,7 +229,6 @@ class FpuTest extends FunSuite{
|
|||
def fmv_w_x(rd : Int, value : Int): Unit ={
|
||||
cmdQueue += {cmd =>
|
||||
cmd.opcode #= cmd.opcode.spinalEnum.FMV_W_X
|
||||
cmd.value.randomize()
|
||||
cmd.rs1.randomize()
|
||||
cmd.rs2.randomize()
|
||||
cmd.rs3.randomize()
|
||||
|
|
@ -256,7 +245,6 @@ class FpuTest extends FunSuite{
|
|||
def min(rd : Int, rs1 : Int, rs2 : Int): Unit ={
|
||||
cmdQueue += {cmd =>
|
||||
cmd.opcode #= cmd.opcode.spinalEnum.MIN_MAX
|
||||
cmd.value.randomize()
|
||||
cmd.rs1 #= rs1
|
||||
cmd.rs2 #= rs2
|
||||
cmd.rs3.randomize()
|
||||
|
|
@ -273,7 +261,6 @@ class FpuTest extends FunSuite{
|
|||
def sgnj(rd : Int, rs1 : Int, rs2 : Int): Unit ={
|
||||
cmdQueue += {cmd =>
|
||||
cmd.opcode #= cmd.opcode.spinalEnum.SGNJ
|
||||
cmd.value.randomize()
|
||||
cmd.rs1 #= rs1
|
||||
cmd.rs2 #= rs2
|
||||
cmd.rs3.randomize()
|
||||
|
|
@ -447,9 +434,11 @@ class FpuTest extends FunSuite{
|
|||
val rd = Random.nextInt(32)
|
||||
i2f(rd, a, signed)
|
||||
storeFloat(rd){v =>
|
||||
val ref = a.toInt
|
||||
println(f"i2f($a) = $v, $ref")
|
||||
assert(v === ref)
|
||||
val aLong = if(signed) a.toLong else a.toLong & 0xFFFFFFFFl
|
||||
val ref = if(signed) a.toFloat else (a.toLong & 0xFFFFFFFFl).toFloat
|
||||
println(f"i2f($aLong) = $v, $ref")
|
||||
if(ref.abs < (1 << 22)) assert(v === ref)
|
||||
assert(checkFloat(v, ref))
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -542,6 +531,65 @@ class FpuTest extends FunSuite{
|
|||
val fNan = List(Float.NaN, b2f(0x7f820000), b2f(0x7fc00000))
|
||||
val fAll = fZeros ++ fSubnormals ++ fExpSmall ++ fExpNormal ++ fExpBig ++ fInfinity ++ fNan
|
||||
|
||||
val iSmall = (0 to 20)
|
||||
val iBigUnsigned = (0 to 20).map(e => 0xFFFFFFFF - e)
|
||||
val iBigSigned = (0 to 20).map(e => 0x7FFFFFFF - e) ++ (0 to 20).map(e => 0x80000000 + e)
|
||||
val iUnsigned = iSmall ++ iBigUnsigned
|
||||
val iSigned = iSmall ++ iSmall.map(-_) ++ iBigSigned
|
||||
|
||||
|
||||
testLoadStore(1.17549435082e-38f)
|
||||
testLoadStore(1.4E-45f)
|
||||
testLoadStore(3.44383110592e-41f)
|
||||
|
||||
testAdd(b2f(0x3f800000), b2f(0x3f800000-1))
|
||||
testAdd(1.1f, 2.3f)
|
||||
testAdd(1.2f, -1.2f)
|
||||
testAdd(-1.2f, 1.2f)
|
||||
testAdd(0.0f, -1.2f)
|
||||
testAdd(-0.0f, -1.2f)
|
||||
testAdd(1.2f, -0f)
|
||||
testAdd(1.2f, 0f)
|
||||
testAdd(1.1f, Float.MinPositiveValue)
|
||||
|
||||
for(a <- fAll; _ <- 0 until 50) testAdd(a, randomFloat())
|
||||
for(b <- fAll; _ <- 0 until 50) testAdd(randomFloat(), b)
|
||||
for(a <- fAll; b <- fAll) testAdd(a, b)
|
||||
for(_ <- 0 until 1000) testAdd(randomFloat(), randomFloat())
|
||||
|
||||
|
||||
|
||||
testLoadStore(1.2f)
|
||||
testMul(1.2f, 2.5f)
|
||||
testMul(b2f(0x00400000), 16.0f)
|
||||
testMul(b2f(0x00100000), 16.0f)
|
||||
testMul(b2f(0x00180000), 16.0f)
|
||||
testMul(b2f(0x00000004), 16.0f)
|
||||
testMul(b2f(0x00000040), 16.0f)
|
||||
testMul(b2f(0x00000041), 16.0f)
|
||||
testMul(b2f(0x00000001), b2f(0x00000001))
|
||||
testMul(1.0f, b2f(0x00000001))
|
||||
testMul(0.5f, b2f(0x00000001))
|
||||
|
||||
// dut.clockDomain.waitSampling(1000)
|
||||
// simSuccess()
|
||||
|
||||
testMul(1.2f, 0f)
|
||||
for(a <- fAll; _ <- 0 until 50) testMul(a, randomFloat())
|
||||
for(b <- fAll; _ <- 0 until 50) testMul(randomFloat(), b)
|
||||
for(a <- fAll; b <- fAll) testMul(a, b)
|
||||
for(_ <- 0 until 1000) testMul(randomFloat(), randomFloat())
|
||||
|
||||
|
||||
|
||||
testLoadStore(1.765f)
|
||||
testFmv_w_x(lang.Float.floatToIntBits(7.234f))
|
||||
testI2f(64, false)
|
||||
for(i <- iUnsigned) testI2f(i, false)
|
||||
for(i <- iSigned) testI2f(i, true)
|
||||
for(_ <- 0 until 1000) testI2f(Random.nextInt(), Random.nextBoolean())
|
||||
|
||||
|
||||
testCmp(0.0f, 1.2f )
|
||||
testCmp(1.2f, 0.0f )
|
||||
testCmp(0.0f, -0.0f )
|
||||
|
|
@ -576,41 +624,6 @@ class FpuTest extends FunSuite{
|
|||
|
||||
|
||||
|
||||
testAdd(b2f(0x3f800000), b2f(0x3f800000-1))
|
||||
testAdd(1.1f, 2.3f)
|
||||
testAdd(1.2f, -1.2f)
|
||||
testAdd(-1.2f, 1.2f)
|
||||
testAdd(0.0f, -1.2f)
|
||||
testAdd(-0.0f, -1.2f)
|
||||
testAdd(1.2f, -0f)
|
||||
testAdd(1.2f, 0f)
|
||||
testAdd(1.1f, Float.MinPositiveValue)
|
||||
|
||||
for(a <- fAll; _ <- 0 until 50) testAdd(a, randomFloat())
|
||||
for(b <- fAll; _ <- 0 until 50) testAdd(randomFloat(), b)
|
||||
for(a <- fAll; b <- fAll) testAdd(a, b)
|
||||
for(_ <- 0 until 1000) testAdd(randomFloat(), randomFloat())
|
||||
|
||||
testLoadStore(1.2f)
|
||||
testMul(1.2f, 2.5f)
|
||||
testMul(b2f(0x00400000), 16.0f)
|
||||
testMul(b2f(0x00100000), 16.0f)
|
||||
testMul(b2f(0x00180000), 16.0f)
|
||||
testMul(b2f(0x00000004), 16.0f)
|
||||
testMul(b2f(0x00000040), 16.0f)
|
||||
testMul(b2f(0x00000041), 16.0f)
|
||||
testMul(b2f(0x00000001), b2f(0x00000001))
|
||||
testMul(1.0f, b2f(0x00000001))
|
||||
testMul(0.5f, b2f(0x00000001))
|
||||
|
||||
// dut.clockDomain.waitSampling(1000)
|
||||
// simSuccess()
|
||||
|
||||
testMul(1.2f, 0f)
|
||||
for(a <- fAll; _ <- 0 until 50) testMul(a, randomFloat())
|
||||
for(b <- fAll; _ <- 0 until 50) testMul(randomFloat(), b)
|
||||
for(a <- fAll; b <- fAll) testMul(a, b)
|
||||
for(_ <- 0 until 1000) testMul(randomFloat(), randomFloat())
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue