Fix DecodingSimplePlugin model building when reinvocation is done one a preexisting opcode.
add Atomic test flow
This commit is contained in:
Dolu1990
parent
468dd3841e
commit
4637e6cb48
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@ -43,11 +43,23 @@ case class Masked(value : BigInt,care : BigInt){
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class DecoderSimplePlugin(catchIllegalInstruction : Boolean, forceLegalInstructionComputation : Boolean = false) extends Plugin[VexRiscv] with DecoderService {
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override def add(encoding: Seq[(MaskedLiteral, Seq[(Stageable[_ <: BaseType], Any)])]): Unit = encoding.foreach(e => this.add(e._1,e._2))
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override def add(key: MaskedLiteral, values: Seq[(Stageable[_ <: BaseType], Any)]): Unit = {
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assert(!encodings.contains(key))
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encodings.getOrElseUpdate(key,ArrayBuffer[(Stageable[_ <: BaseType], BaseType)]()) ++= values.map{case (a,b) => (a,b match{
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// val instructionModel = encodings.getOrElseUpdate(key,ArrayBuffer[(Stageable[_ <: BaseType], BaseType)]())
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val instructionModel = encodings.find(x => x._1.careAbout == key.careAbout && x._1.width == key.width && x._1.value == key.value) match {
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case Some(x) => x._2
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case _ => {
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val model = ArrayBuffer[(Stageable[_ <: BaseType], BaseType)]()
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encodings.put(key, model)
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model
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}
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}
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values.map{case (a,b) => {
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assert(!instructionModel.contains(a), s"Over specification of $a")
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val value = b match {
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case e: SpinalEnumElement[_] => e()
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case e: BaseType => e
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})}
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}
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instructionModel += (a->value)
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}}
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}
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override def addDefault(key: Stageable[_ <: BaseType], value: Any): Unit = {
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@ -0,0 +1,44 @@
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build/atomic.elf: file format elf32-littleriscv
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Disassembly of section .crt_section:
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00000000 <_start>:
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0: 00100e13 li t3,1
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4: 10000537 lui a0,0x10000
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8: 06400593 li a1,100
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c: 06500613 li a2,101
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10: 06600693 li a3,102
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14: 00d52023 sw a3,0(a0) # 10000000 <pass+0xfffffa0>
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18: 18b5262f sc.w a2,a1,(a0)
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1c: 02060c63 beqz a2,54 <fail>
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20: 00052703 lw a4,0(a0)
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24: 02e69863 bne a3,a4,54 <fail>
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28: 00200e13 li t3,2
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2c: 10000537 lui a0,0x10000
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30: 06400593 li a1,100
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34: 06500613 li a2,101
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38: 06600693 li a3,102
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3c: 00d52023 sw a3,0(a0) # 10000000 <pass+0xfffffa0>
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40: 18b5262f sc.w a2,a1,(a0)
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44: 00060863 beqz a2,54 <fail>
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48: 00052703 lw a4,0(a0)
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4c: 00e69463 bne a3,a4,54 <fail>
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50: 0100006f j 60 <pass>
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00000054 <fail>:
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54: f0100137 lui sp,0xf0100
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58: f2410113 addi sp,sp,-220 # f00fff24 <pass+0xf00ffec4>
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5c: 01c12023 sw t3,0(sp)
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00000060 <pass>:
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60: f0100137 lui sp,0xf0100
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64: f2010113 addi sp,sp,-224 # f00fff20 <pass+0xf00ffec0>
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68: 00012023 sw zero,0(sp)
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6c: 00000013 nop
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70: 00000013 nop
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74: 00000013 nop
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78: 00000013 nop
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7c: 00000013 nop
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80: 00000013 nop
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Binary file not shown.
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@ -0,0 +1,10 @@
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:10000000130E100037050010930540061306500626
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:10001000930660062320D5002F26B518630C060230
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:10002000032705006398E602130E20003705001031
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:100030009305400613065006930660062320D5005C
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:100040002F26B51863080600032705006394E60011
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:100050006F000001370110F0130141F22320C101AC
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:10006000370110F0130101F22320010013000000FA
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:100070001300000013000000130000001300000034
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:040080001300000069
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:00000001FF
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@ -0,0 +1,30 @@
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Memory Configuration
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Name Origin Length Attributes
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onChipRam 0x0000000000000000 0x0000000000002000 w !xr
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*default* 0x0000000000000000 0xffffffffffffffff
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Linker script and memory map
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LOAD build/src/crt.o
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LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.1.1/libgcc.a
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START GROUP
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LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.1.1/../../../../riscv64-unknown-elf/lib/libc.a
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LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.1.1/../../../../riscv64-unknown-elf/lib/libgloss.a
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END GROUP
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LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.1.1/libgcc.a
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0x0000000000000000 . = 0x0
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.crt_section 0x0000000000000000 0x84
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0x0000000000000000 . = ALIGN (0x4)
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*crt.o(.text)
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.text 0x0000000000000000 0x84 build/src/crt.o
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0x0000000000000000 _start
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OUTPUT(build/atomic.elf elf32-littleriscv)
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.data 0x0000000000000084 0x0
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.data 0x0000000000000084 0x0 build/src/crt.o
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.bss 0x0000000000000084 0x0
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.bss 0x0000000000000084 0x0 build/src/crt.o
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@ -0,0 +1,10 @@
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@00000000
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13 0E 10 00 37 05 00 10 93 05 40 06 13 06 50 06
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93 06 60 06 23 20 D5 00 2F 26 B5 18 63 0C 06 02
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03 27 05 00 63 98 E6 02 13 0E 20 00 37 05 00 10
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93 05 40 06 13 06 50 06 93 06 60 06 23 20 D5 00
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2F 26 B5 18 63 08 06 00 03 27 05 00 63 94 E6 00
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6F 00 00 01 37 01 10 F0 13 01 41 F2 23 20 C1 01
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37 01 10 F0 13 01 01 F2 23 20 01 00 13 00 00 00
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13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00
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13 00 00 00
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@ -0,0 +1,73 @@
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PROJ_NAME=atomic
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RISCV_PATH=/opt/riscv/
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CFLAGS += -march=rv32ia -mabi=ilp32
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RISCV_NAME = riscv64-unknown-elf
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RISCV_OBJCOPY = $(RISCV_PATH)/bin/$(RISCV_NAME)-objcopy
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RISCV_OBJDUMP = $(RISCV_PATH)/bin/$(RISCV_NAME)-objdump
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RISCV_CLIB=$(RISCV_PATH)$(RISCV_NAME)/lib/
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RISCV_CC=$(RISCV_PATH)/bin/$(RISCV_NAME)-gcc
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LDSCRIPT=src/ld
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SRCS = $(wildcard src/*.c) \
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$(wildcard src/*.cpp) \
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$(wildcard src/*.S)
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CFLAGS += -static
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LDFLAGS += -e_start -T $(LDSCRIPT) -nostartfiles -Wl,-Map,$(OBJDIR)/$(PROJ_NAME).map -Wl,--print-memory-usage
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OBJDIR = build
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OBJS := $(SRCS)
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OBJS := $(OBJS:.c=.o)
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OBJS := $(OBJS:.cpp=.o)
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OBJS := $(OBJS:.S=.o)
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OBJS := $(addprefix $(OBJDIR)/,$(OBJS))
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all: $(OBJDIR)/$(PROJ_NAME).elf $(OBJDIR)/$(PROJ_NAME).hex $(OBJDIR)/$(PROJ_NAME).asm $(OBJDIR)/$(PROJ_NAME).v
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@echo "done"
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$(OBJDIR)/%.elf: $(OBJS) | $(OBJDIR)
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$(RISCV_CC) $(CFLAGS) -o $@ $^ $(LDFLAGS) $(LIBS)
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%.hex: %.elf
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$(RISCV_OBJCOPY) -O ihex $^ $@
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%.bin: %.elf
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$(RISCV_OBJCOPY) -O binary $^ $@
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%.v: %.elf
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$(RISCV_OBJCOPY) -O verilog $^ $@
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%.asm: %.elf
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$(RISCV_OBJDUMP) -S -d $^ > $@
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$(OBJDIR)/%.o: %.c
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mkdir -p $(dir $@)
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$(RISCV_CC) -c $(CFLAGS) $(INC) -o $@ $^
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$(OBJDIR)/%.o: %.cpp
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mkdir -p $(dir $@)
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$(RISCV_CC) -c $(CFLAGS) $(INC) -o $@ $^
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$(OBJDIR)/%.o: %.S
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mkdir -p $(dir $@)
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$(RISCV_CC) -c $(CFLAGS) -o $@ $^ -D__ASSEMBLY__=1
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$(OBJDIR):
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mkdir -p $@
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clean:
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rm -f $(OBJDIR)/$(PROJ_NAME).elf
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rm -f $(OBJDIR)/$(PROJ_NAME).hex
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rm -f $(OBJDIR)/$(PROJ_NAME).map
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rm -f $(OBJDIR)/$(PROJ_NAME).v
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rm -f $(OBJDIR)/$(PROJ_NAME).asm
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find $(OBJDIR) -type f -name '*.o' -print0 | xargs -0 -r rm
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.SECONDARY: $(OBJS)
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@ -0,0 +1,50 @@
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.globl _start
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_start:
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//Test 1 SC on unreserved area should fail and not write memory
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li x28, 1
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li a0, 0x10000000
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li a1, 100
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li a2, 101
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li a3, 102
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sw a3, 0(a0)
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sc.w a2, a1, (a0)
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beq a2, x0, fail
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lw a4, 0(a0)
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bne a3, a4, fail
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//Test 2 retrying SC on unreserved area should fail and not write memory
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li x28, 2
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li a0, 0x10000000
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li a1, 100
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li a2, 101
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li a3, 102
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sw a3, 0(a0)
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sc.w a2, a1, (a0)
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beq a2, x0, fail
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lw a4, 0(a0)
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bne a3, a4, fail
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j pass
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fail: //x28 => error code
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li x2, 0xF00FFF24
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sw x28, 0(x2)
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pass:
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li x2, 0xF00FFF20
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sw x0, 0(x2)
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nop
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nop
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nop
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nop
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nop
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nop
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@ -0,0 +1,17 @@
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OUTPUT_ARCH( "riscv" )
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MEMORY {
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onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x00000000, LENGTH = 8K
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}
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SECTIONS
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{
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. = 0x000;
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.crt_section :
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{
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. = ALIGN(4);
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*crt.o(.text)
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} > onChipRam
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}
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@ -1725,6 +1725,11 @@ int main(int argc, char **argv, char **env) {
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redo(REDO,Workspace("custom_simd_add").loadHex("../custom/simd_add/build/custom_simd_add.hex")->bootAt(0x00000000u)->run(50e3););
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#endif
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#ifdef ATOMIC
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redo(REDO,Workspace("atomic").loadHex("../custom/atomic/build/atomic.hex")->bootAt(0x00000000u)->run(50e3););
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#endif
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#ifdef DHRYSTONE
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Dhrystone("dhrystoneO3_Stall","dhrystoneO3",true,true).run(1.1e6);
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#if defined(MUL) && defined(DIV)
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@ -8,6 +8,7 @@ MUL?=yes
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DIV?=yes
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CSR?=yes
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MMU?=yes
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ATOMIC?=no
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DEBUG_PLUGIN?=STD
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DEBUG_PLUGIN_EXTERNAL?=no
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CUSTOM_SIMD_ADD?=no
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@ -38,6 +39,11 @@ ifeq ($(CSR),yes)
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ADDCFLAGS += -CFLAGS -DCSR
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endif
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ifeq ($(ATOMIC),yes)
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ADDCFLAGS += -CFLAGS -DATOMIC
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endif
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ifeq ($(CUSTOM_SIMD_ADD),yes)
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ADDCFLAGS += -CFLAGS -DCUSTOM_SIMD_ADD
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endif
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