Updates two missed issues with nativeJtag documentation from previous commit.
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# AcceleoIssueWithInvalids
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https://www.eclipse.org/forums/index.php/t/1091946/
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# DELETE THIS AFTER
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# Implementing VexRiscv Based Murax SoC on Arty A7 Artix-7 PCB from Digilent and Enabling JTAG Connection through Xilinx’s BSCANE2 Debug IP
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**By**<br>
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