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Add VexRiscvSmpCluster forceMisa/forceMscratch

This commit is contained in:
Dolu1990 2022-05-23 15:49:32 +02:00
parent 0872852387
commit 48cf4120f2
1 changed files with 6 additions and 4 deletions
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10
src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
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@ -192,7 +192,9 @@ object VexRiscvSmpClusterGen {
dTlbSize : Int = 4, dTlbSize : Int = 4,
prediction : BranchPrediction = vexriscv.plugin.NONE, prediction : BranchPrediction = vexriscv.plugin.NONE,
withDataCache : Boolean = true, withDataCache : Boolean = true,
withInstructionCache : Boolean = true withInstructionCache : Boolean = true,
forceMisa : Boolean = false,
forceMscratch : Boolean = false
) = { ) = {
assert(iCacheSize/iCacheWays <= 4096, "Instruction cache ways can't be bigger than 4096 bytes") assert(iCacheSize/iCacheWays <= 4096, "Instruction cache ways can't be bigger than 4096 bytes")
assert(dCacheSize/dCacheWays <= 4096, "Data cache ways can't be bigger than 4096 bytes") assert(dCacheSize/dCacheWays <= 4096, "Data cache ways can't be bigger than 4096 bytes")
@ -207,12 +209,12 @@ object VexRiscvSmpClusterGen {
marchid = null, marchid = null,
mimpid = null, mimpid = null,
mhartid = hartId, mhartid = hartId,
misaExtensionsInit = 0, misaExtensionsInit = Riscv.misaToInt(s"ima${if(withFloat) "f" else ""}${if(withDouble) "d" else ""}s"),
misaAccess = CsrAccess.NONE, misaAccess = if(forceMisa) CsrAccess.WRITE_ONLY else CsrAccess.NONE,
mtvecAccess = CsrAccess.READ_WRITE, mtvecAccess = CsrAccess.READ_WRITE,
mtvecInit = null, mtvecInit = null,
mepcAccess = CsrAccess.READ_WRITE, mepcAccess = CsrAccess.READ_WRITE,
mscratchGen = false, mscratchGen = forceMscratch,
mcauseAccess = CsrAccess.READ_ONLY, mcauseAccess = CsrAccess.READ_ONLY,
mbadaddrAccess = CsrAccess.READ_ONLY, mbadaddrAccess = CsrAccess.READ_ONLY,
mcycleAccess = CsrAccess.NONE, mcycleAccess = CsrAccess.NONE,