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DBusCachedPlugin fix noWriteBack redo priority

This commit is contained in:
Charles Papon 2020-02-28 17:21:59 +01:00
parent 76d063f20a
commit 492310e6fa
4 changed files with 12 additions and 10 deletions
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2
src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
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@ -145,7 +145,7 @@ class DBusCachedPlugin(val config : DataCacheConfig,
decoderService.add(FENCE, Nil)
mmuBus = pipeline.service(classOf[MemoryTranslator]).newTranslationPort(MemoryTranslatorPort.PRIORITY_DATA ,memoryTranslatorPortConfig)
redoBranch = pipeline.service(classOf[JumpService]).createJumpInterface(if(pipeline.writeBack != null) pipeline.writeBack else pipeline.execute)
redoBranch = pipeline.service(classOf[JumpService]).createJumpInterface(if(pipeline.writeBack != null) pipeline.writeBack else pipeline.memory)
if(catchSomething)
exceptionBus = pipeline.service(classOf[ExceptionService]).newExceptionPort(if(pipeline.writeBack == null) pipeline.memory else pipeline.writeBack)

4
src/main/scala/vexriscv/plugin/Fetcher.scala
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@ -159,7 +159,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
}
pc(0) := False
if(!pipeline(RVC_GEN)) pc(1) := False
if(!compressedGen) pc(1) := False
output.valid := !fetcherHalt && booted
output.payload := pc
@ -590,7 +590,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
val compressor = compressedGen generate new Area{
val predictionBranch = iBusRspContext.hit && !iBusRspContext.hazard && iBusRspContext.line.branchWish(1)
val unalignedWordIssue = iBusRsp.output.valid && predictionBranch && decompressor.throw2Bytes && !decompressor.isInputHighRvc
val unalignedWordIssue = iBusRsp.output.valid && predictionBranch && iBusRspContext.line.last2Bytes && Mux(decompressor.unaligned, !decompressor.isInputHighRvc, decompressor.isInputLowRvc && !decompressor.isInputHighRvc)
when(unalignedWordIssue){
historyWrite.valid := True

2
src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
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@ -343,7 +343,7 @@ class IBusSimplePlugin( resetVector : BigInt,
//Manage flush for iBus transactions in flight
val discardCounter = Reg(UInt(log2Up(pendingMax + 1) bits)) init (0)
discardCounter := discardCounter - (iBus.rsp.fire && discardCounter =/= 0).asUInt
when(fetcherflushIt) {
when(iBusRsp.stages.last.flush) {
if(secondStagePersistence)
discardCounter := pendingCmd + cmd.valid.asUInt - iBus.rsp.fire.asUInt
else

14
src/test/scala/vexriscv/TestIndividualFeatures.scala
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@ -628,13 +628,15 @@ class TestIndividualFeatures extends FunSuite {
}
}
val testId : Option[mutable.HashSet[Int]] = None
val seed = sys.env.getOrElse("VEXRISCV_REGRESSION_SEED", Random.nextLong().toString).toLong
//
var testId : Option[mutable.HashSet[Int]] = None
var seed = sys.env.getOrElse("VEXRISCV_REGRESSION_SEED", Random.nextInt(1000000000).toString).toLong
// val testId = Some(mutable.HashSet(3,4,9,11,13,16,18,19,20,21))
// val testId = Some(mutable.HashSet(11))
// val testId = Some(mutable.HashSet(6))
// val seed = 9095713085965080531l
// val testId = Some(mutable.HashSet(15))
// seed = -7374992264756372315l
// testId = Some(mutable.HashSet(1,2,6,14,15,16,19))
// testId = Some(mutable.HashSet(1,2,6,14))
// testId = Some(mutable.HashSet(1))
val rand = new Random(seed)