Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

CsrPlugin: insert FORMAL_HALT := False

This commit is contained in:
Leon Schuermann 2023-02-24 16:34:06 -05:00
parent 366f09a14a
commit 49246e757f
1 changed files with 4 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/vexriscv/plugin/CsrPlugin.scala
View File

@ -670,6 +670,10 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
} }
} }
// The CSR plugin will invoke a trap handler on exception, which does not
// count as halt-state by the RVFI spec, and neither do other instructions
// such as `wfi`, etc. Hence statically drive the output:
pipeline.stages.head.insert(FORMAL_HALT) := False
case class Xtvec() extends Bundle { case class Xtvec() extends Bundle {
val mode = Bits(2 bits) val mode = Bits(2 bits)