pipeline data cache unaligned access check
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4c3cad97d3
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@ -157,7 +157,8 @@ object VexRiscvSmpClusterGen {
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iCacheSize : Int = 8192,
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dCacheSize : Int = 8192,
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iCacheWays : Int = 2,
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dCacheWays : Int = 2) = {
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dCacheWays : Int = 2,
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iBusRelax : Boolean = false) = {
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assert(iCacheSize/iCacheWays <= 4096, "Instruction cache ways can't be bigger than 4096 bytes")
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assert(dCacheSize/dCacheWays <= 4096, "Data cache ways can't be bigger than 4096 bytes")
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val config = VexRiscvConfig(
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@ -173,7 +174,7 @@ object VexRiscvSmpClusterGen {
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historyRamSizeLog2 = 9,
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relaxPredictorAddress = true,
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injectorStage = false,
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relaxedPcCalculation = false,
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relaxedPcCalculation = iBusRelax,
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config = InstructionCacheConfig(
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cacheSize = iCacheSize,
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bytePerLine = 64,
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@ -791,6 +791,7 @@ class DataCache(val p : DataCacheConfig, mmuParameter : MemoryTranslatorBusParam
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val wayInvalidate = stagePipe(stageA. wayInvalidate)
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val consistancyHazard = if(stageA.consistancyCheck != null) stagePipe(stageA.consistancyCheck.hazard) else False
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val dataColisions = stagePipe(stageA.dataColisions)
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val unaligned = if(!catchUnaligned) False else stagePipe((stageA.request.size === 2 && io.cpu.memory.address(1 downto 0) =/= 0) || (stageA.request.size === 1 && io.cpu.memory.address(0 downto 0) =/= 0))
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val waysHitsBeforeInvalidate = if(earlyWaysHits) stagePipe(B(stageA.wayHits)) else B(tagsReadRsp.map(tag => mmuRsp.physicalAddress(tagRange) === tag.address && tag.valid).asBits())
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val waysHits = waysHitsBeforeInvalidate & ~wayInvalidate
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val waysHit = waysHits.orR
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@ -891,7 +892,7 @@ class DataCache(val p : DataCacheConfig, mmuParameter : MemoryTranslatorBusParam
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io.cpu.redo := False
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io.cpu.writeBack.accessError := False
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io.cpu.writeBack.mmuException := io.cpu.writeBack.isValid && (if(catchIllegal) mmuRsp.exception || (!mmuRsp.allowWrite && request.wr) || (!mmuRsp.allowRead && (!request.wr || isAmo)) else False)
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io.cpu.writeBack.unalignedAccess := io.cpu.writeBack.isValid && (if(catchUnaligned) ((request.size === 2 && mmuRsp.physicalAddress(1 downto 0) =/= 0) || (request.size === 1 && mmuRsp.physicalAddress(0 downto 0) =/= 0)) else False)
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io.cpu.writeBack.unalignedAccess := io.cpu.writeBack.isValid && unaligned
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io.cpu.writeBack.isWrite := request.wr
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io.mem.cmd.valid := False
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