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pipeline data cache unaligned access check

This commit is contained in:
Dolu1990 2020-09-07 12:01:03 +02:00
parent 4c3cad97d3
commit 49488d19af
2 changed files with 5 additions and 3 deletions
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5
src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
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@ -157,7 +157,8 @@ object VexRiscvSmpClusterGen {
iCacheSize : Int = 8192, iCacheSize : Int = 8192,
dCacheSize : Int = 8192, dCacheSize : Int = 8192,
iCacheWays : Int = 2, iCacheWays : Int = 2,
dCacheWays : Int = 2) = { dCacheWays : Int = 2,
iBusRelax : Boolean = false) = {
assert(iCacheSize/iCacheWays <= 4096, "Instruction cache ways can't be bigger than 4096 bytes") assert(iCacheSize/iCacheWays <= 4096, "Instruction cache ways can't be bigger than 4096 bytes")
assert(dCacheSize/dCacheWays <= 4096, "Data cache ways can't be bigger than 4096 bytes") assert(dCacheSize/dCacheWays <= 4096, "Data cache ways can't be bigger than 4096 bytes")
val config = VexRiscvConfig( val config = VexRiscvConfig(
@ -173,7 +174,7 @@ object VexRiscvSmpClusterGen {
historyRamSizeLog2 = 9, historyRamSizeLog2 = 9,
relaxPredictorAddress = true, relaxPredictorAddress = true,
injectorStage = false, injectorStage = false,
relaxedPcCalculation = false, relaxedPcCalculation = iBusRelax,
config = InstructionCacheConfig( config = InstructionCacheConfig(
cacheSize = iCacheSize, cacheSize = iCacheSize,
bytePerLine = 64, bytePerLine = 64,

3
src/main/scala/vexriscv/ip/DataCache.scala
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@ -791,6 +791,7 @@ class DataCache(val p : DataCacheConfig, mmuParameter : MemoryTranslatorBusParam
val wayInvalidate = stagePipe(stageA. wayInvalidate) val wayInvalidate = stagePipe(stageA. wayInvalidate)
val consistancyHazard = if(stageA.consistancyCheck != null) stagePipe(stageA.consistancyCheck.hazard) else False val consistancyHazard = if(stageA.consistancyCheck != null) stagePipe(stageA.consistancyCheck.hazard) else False
val dataColisions = stagePipe(stageA.dataColisions) val dataColisions = stagePipe(stageA.dataColisions)
val unaligned = if(!catchUnaligned) False else stagePipe((stageA.request.size === 2 && io.cpu.memory.address(1 downto 0) =/= 0) || (stageA.request.size === 1 && io.cpu.memory.address(0 downto 0) =/= 0))
val waysHitsBeforeInvalidate = if(earlyWaysHits) stagePipe(B(stageA.wayHits)) else B(tagsReadRsp.map(tag => mmuRsp.physicalAddress(tagRange) === tag.address && tag.valid).asBits()) val waysHitsBeforeInvalidate = if(earlyWaysHits) stagePipe(B(stageA.wayHits)) else B(tagsReadRsp.map(tag => mmuRsp.physicalAddress(tagRange) === tag.address && tag.valid).asBits())
val waysHits = waysHitsBeforeInvalidate & ~wayInvalidate val waysHits = waysHitsBeforeInvalidate & ~wayInvalidate
val waysHit = waysHits.orR val waysHit = waysHits.orR
@ -891,7 +892,7 @@ class DataCache(val p : DataCacheConfig, mmuParameter : MemoryTranslatorBusParam
io.cpu.redo := False io.cpu.redo := False
io.cpu.writeBack.accessError := False io.cpu.writeBack.accessError := False
io.cpu.writeBack.mmuException := io.cpu.writeBack.isValid && (if(catchIllegal) mmuRsp.exception || (!mmuRsp.allowWrite && request.wr) || (!mmuRsp.allowRead && (!request.wr || isAmo)) else False) io.cpu.writeBack.mmuException := io.cpu.writeBack.isValid && (if(catchIllegal) mmuRsp.exception || (!mmuRsp.allowWrite && request.wr) || (!mmuRsp.allowRead && (!request.wr || isAmo)) else False)
io.cpu.writeBack.unalignedAccess := io.cpu.writeBack.isValid && (if(catchUnaligned) ((request.size === 2 && mmuRsp.physicalAddress(1 downto 0) =/= 0) || (request.size === 1 && mmuRsp.physicalAddress(0 downto 0) =/= 0)) else False) io.cpu.writeBack.unalignedAccess := io.cpu.writeBack.isValid && unaligned
io.cpu.writeBack.isWrite := request.wr io.cpu.writeBack.isWrite := request.wr
io.mem.cmd.valid := False io.mem.cmd.valid := False