fpu fix cmd / commit race condition
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Dolu1990
parent
636d53cf63
commit
4bdab667cc
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@ -121,11 +121,12 @@ object TestsWorkspace {
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// cd buildroot-build/
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// make O=$PWD BR2_EXTERNAL=../buildroot-spinal-saxon -C ../buildroot saxon_regression_defconfig
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//make clean all IBUS=CACHED IBUS_DATA_WIDTH=64 COMPRESSED=no DBUS=CACHED DBUS_LOAD_DATA_WIDTH=64 DBUS_STORE_DATA_WIDTH=64 LRSC=yes AMO=yes SUPERVISOR=yes DBUS_EXCLUSIVE=yes DBUS_INVALIDATE=yes MUL=yes DIV=yes RVF=yes RVD=yes DEBUG_PLUGIN=no TRACE=yes REDO=1 DEBUG=ye WITH_USER_IO=no FLOW_INFO=no TRACE_START=565000000000ll SEED=45
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//make clean all IBUS=CACHED IBUS_DATA_WIDTH=64 COMPRESSED=no DBUS=CACHED DBUS_LOAD_DATA_WIDTH=64 DBUS_STORE_DATA_WIDTH=64 LRSC=yes AMO=yes SUPERVISOR=yes DBUS_EXCLUSIVE=yes DBUS_INVALIDATE=yes MUL=yes DIV=yes RVF=yes RVD=yes DEBUG_PLUGIN=no TRACE=yes REDO=100 DEBUG=ye WITH_USER_IO=no FLOW_INFO=no TRACE_START=5600000000000ll SEED=45 STOP_ON_ERROR=ye
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// export IMAGES=/media/data/open/SaxonSoc/artyA7SmpUpdate/buildroot-regression/buildroot-build/images
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// make clean all IBUS=CACHED IBUS_DATA_WIDTH=64 COMPRESSED=no DBUS=CACHED DBUS_LOAD_DATA_WIDTH=64 DBUS_STORE_DATA_WIDTH=64 LRSC=yes AMO=yes SUPERVISOR=yes DBUS_EXCLUSIVE=yes DBUS_INVALIDATE=yes MUL=yes DIV=yes RVF=yes RVD=yes DEBUG_PLUGIN=no LINUX_SOC_SMP=yes EMULATOR=$IMAGES/fw_jump.bin VMLINUX=$IMAGES/Image DTB=$IMAGES/linux.dtb RAMDISK=$IMAGES/rootfs.cpio TRACE=ye REDO=1 DEBUG=ye WITH_USER_IO=no
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// make clean all IBUS=CACHED IBUS_DATA_WIDTH=64 COMPRESSED=no DBUS=CACHED DBUS_LOAD_DATA_WIDTH=64 DBUS_STORE_DATA_WIDTH=64 LRSC=yes AMO=yes SUPERVISOR=yes DBUS_EXCLUSIVE=yes DBUS_INVALIDATE=yes MUL=yes DIV=yes RVF=yes RVD=yes DEBUG_PLUGIN=no LINUX_SOC_SMP=yes EMULATOR=$IMAGES/fw_jump.bin VMLINUX=$IMAGES/Image DTB=$IMAGES/linux.dtb RAMDISK=$IMAGES/rootfs.cpio TRACE=yes REDO=1 DEBUG=ye WITH_USER_IO=no FLOW_INFO=yes TRACE_START=47000000000ll SEED=43
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// make clean all IBUS=CACHED IBUS_DATA_WIDTH=64 COMPRESSED=no DBUS=CACHED DBUS_LOAD_DATA_WIDTH=64 DBUS_STORE_DATA_WIDTH=64 LRSC=yes AMO=yes SUPERVISOR=yes DBUS_EXCLUSIVE=yes DBUS_INVALIDATE=yes MUL=yes DIV=yes RVF=yes RVD=yes DEBUG_PLUGIN=no LINUX_SOC_SMP=yes EMULATOR=$IMAGES/fw_jump.bin VMLINUX=$IMAGES/Image DTB=$IMAGES/linux.dtb RAMDISK=$IMAGES/rootfs.cpio TRACE=yes REDO=1 DEBUG=ye WITH_USER_IO=no FLOW_INFO=yes TRACE_START=47000000000ll SEED=45
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//make clean all IBUS=CACHED IBUS_DATA_WIDTH=64 COMPRESSED=no DBUS=CACHED DBUS_LOAD_DATA_WIDTH=64 DBUS_STORE_DATA_WIDTH=64 LRSC=yes AMO=yes SUPERVISOR=yes DBUS_EXCLUSIVE=yes DBUS_INVALIDATE=yes MUL=yes DIV=yes RVF=yes RVD=yes DEBUG_PLUGIN=no LINUX_SOC_SMP=yes EMULATOR=$IMAGES/fw_jump.bin VMLINUX=$IMAGES/Image DTB=$IMAGES/linux.dtb RAMDISK=$IMAGES/rootfs.cpio TRACE=yes REDO=1 DEBUG=ye WITH_USER_IO=no FLOW_INFO=yes TRACE_START=565000000ll SEED=45
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// make clean all IBUS=CACHED IBUS_DATA_WIDTH=64 COMPRESSED=no DBUS=CACHED DBUS_LOAD_DATA_WIDTH=64 DBUS_STORE_DATA_WIDTH=64 LRSC=yes AMO=yes SUPERVISOR=yes DBUS_EXCLUSIVE=yes DBUS_INVALIDATE=yes MUL=yes DIV=yes RVF=yes RVD=yes DEBUG_PLUGIN=no LINUX_SOC_SMP=yes EMULATOR=$IMAGES/fw_jump.bin VMLINUX=$IMAGES/Image DTB=$IMAGES/linux.dtb RAMDISK=$IMAGES/rootfs.cpio TRACE=yes REDO=1 DEBUG=ye WITH_USER_IO=no FLOW_INFO=no TRACE_START=565000000000ll SEED=45
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val config = VexRiscvSmpClusterGen.vexRiscvConfig(
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hartId = 0,
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ioRange = _ (31 downto 28) === 0xF,
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@ -139,7 +140,8 @@ object TestsWorkspace {
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dCacheWays = 2,
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withFloat = true,
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withDouble = true,
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externalFpu = false
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externalFpu = false,
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simHalt = true
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)
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@ -167,7 +167,8 @@ object VexRiscvSmpClusterGen {
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withSupervisor : Boolean = true,
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withFloat : Boolean = false,
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withDouble : Boolean = false,
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externalFpu : Boolean = true
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externalFpu : Boolean = true,
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simHalt : Boolean = false
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) = {
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assert(iCacheSize/iCacheWays <= 4096, "Instruction cache ways can't be bigger than 4096 bytes")
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assert(dCacheSize/dCacheWays <= 4096, "Data cache ways can't be bigger than 4096 bytes")
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@ -280,6 +281,7 @@ object VexRiscvSmpClusterGen {
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if(withFloat) config.plugins += new FpuPlugin(
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externalFpu = externalFpu,
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simHalt = simHalt,
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p = FpuParameter(withDouble = withDouble)
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)
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config
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@ -179,25 +179,10 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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})
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}
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// val completion = for(source <- 0 until portCount) yield new Area{
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// def port = io.port(source)
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// port.completion.flag.NV := False
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// port.completion.flag.DZ := False
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// port.completion.flag.OF := False
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// port.completion.flag.UF := False
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// port.completion.flag.NX := False
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//
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// val increments = ArrayBuffer[Bool]()
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//
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// afterElaboration{
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// port.completion.count := increments.map(_.asUInt.resize(log2Up(increments.size + 1))).reduceBalancedTree(_ + _)
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// }
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// }
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val commitFork = new Area{
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val load, commit = Vec(Stream(FpuCommit(p)), portCount)
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for(i <- 0 until portCount){
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val fork = new StreamFork(FpuCommit(p), 2)
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val fork = new StreamFork(FpuCommit(p), 2, synchronous = true)
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fork.io.input << io.port(i).commit
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fork.io.outputs(0) >> load(i)
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fork.io.outputs(1).pipelined(m2s = true, s2m = true) >> commit(i) //Pipelining here is light, as it only use the flags of the payload
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@ -214,8 +199,9 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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}
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class CommitArea(source : Int) extends Area{
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val pending = new Tracker(4)
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val add, mul, div, sqrt, short = new Tracker(4)
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val input = commitFork.commit(source).haltWhen(List(add, mul, div, sqrt, short).map(_.full).orR).toFlow
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val input = commitFork.commit(source).haltWhen(List(add, mul, div, sqrt, short).map(_.full).orR || !pending.notEmpty).toFlow
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when(input.fire){
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add.inc setWhen(List(FpuOpcode.ADD).map(input.opcode === _).orR)
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@ -224,6 +210,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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sqrt.inc setWhen(List(FpuOpcode.SQRT).map(input.opcode === _).orR)
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short.inc setWhen(List(FpuOpcode.SGNJ, FpuOpcode.MIN_MAX, FpuOpcode.FCVT_X_X).map(input.opcode === _).orR)
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rf.scoreboards(source).writes(input.rd) := input.write
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pending.dec := True
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}
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}
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@ -237,7 +224,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val scheduler = for(portId <- 0 until portCount;
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scoreboard = rf.scoreboards(portId)) yield new Area{
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val input = io.port(portId).cmd.combStage()
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val input = io.port(portId).cmd.pipelined(s2m = true)
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val useRs1, useRs2, useRs3, useRd = False
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switch(input.opcode){
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is(p.Opcode.LOAD) { useRd := True }
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@ -265,7 +252,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val rfBusy = (rfHits, rfTargets).zipped.map(_ ^ _)
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val hits = (0 to 3).map(id => uses(id) && rfBusy(id))
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val hazard = hits.orR || !rf.init.done
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val hazard = hits.orR || !rf.init.done || commitLogic(portId).pending.full
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val output = input.haltWhen(hazard)
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when(input.valid && rf.init.done){
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scoreboard.targetWrite.address := input.rd
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@ -273,6 +260,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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}
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when(output.fire && useRd){
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scoreboard.targetWrite.valid := True
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commitLogic(portId).pending.inc := True
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}
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}
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@ -287,7 +275,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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}
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val read = new Area{
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val s0 = cmdArbiter.output.pipelined(m2s = true, s2m = true) //TODO may need to remove m2s for store latency
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val s0 = cmdArbiter.output.pipelined() //TODO may need to remove m2s for store latency
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val s1 = s0.m2sPipe()
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val output = s1.swapPayload(RfReadOutput())
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val rs1Entry = rf.ram.readSync(s0.source @@ s0.rs1,enable = !output.isStall)
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@ -982,7 +970,6 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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when(exp(exp.getWidth-3, 3 bits) >= 5) { output.exponent(p.internalExponentSize-2, 2 bits) := 3 }
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// val flag = io.port(input.source).completion.flag
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when(forceNan) {
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output.setNanQuiet
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NV setWhen(infinitynan || input.rs1.isNanSignaling || input.rs2.isNanSignaling)
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@ -1479,8 +1466,6 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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if (p.withDouble) output.format := input.format
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output.scrap := (mantissa(1) | mantissa(0) | roundingScrap)
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// val flag = io.port(input.source).completion.flag
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output.NV := infinityNan || input.rs1.isNanSignaling || input.rs2.isNanSignaling
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output.DZ := False
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when(forceNan) {
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@ -10,6 +10,7 @@ import vexriscv.ip.fpu._
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import scala.collection.mutable.ArrayBuffer
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class FpuPlugin(externalFpu : Boolean = false,
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simHalt : Boolean = false,
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p : FpuParameter) extends Plugin[VexRiscv] with VexRiscvRegressionArg {
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object FPU_ENABLE extends Stageable(Bool())
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@ -222,10 +223,20 @@ class FpuPlugin(externalFpu : Boolean = false,
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val internal = (!externalFpu).generate (pipeline plug new Area{
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val fpu = FpuCore(1, p)
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if(simHalt) {
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val cmdHalt = in(Bool).setName("fpuCmdHalt").addAttribute(Verilator.public)
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val commitHalt = in(Bool).setName("fpuCommitHalt").addAttribute(Verilator.public)
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val rspHalt = in(Bool).setName("fpuRspHalt").addAttribute(Verilator.public)
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fpu.io.port(0).cmd << port.cmd.haltWhen(cmdHalt)
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fpu.io.port(0).commit << port.commit.haltWhen(commitHalt)
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fpu.io.port(0).rsp.haltWhen(rspHalt) >> port.rsp
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fpu.io.port(0).completion <> port.completion
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} else {
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fpu.io.port(0).cmd << port.cmd
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fpu.io.port(0).commit << port.commit
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fpu.io.port(0).rsp >> port.rsp
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fpu.io.port(0).completion <> port.completion
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}
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})
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@ -1848,6 +1848,11 @@ public:
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instanceCycles += 1;
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for(SimElement* simElement : simElements) simElement->postCycle();
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#ifdef RVF
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top->fpuCmdHalt = VL_RANDOM_I(1);
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top->fpuCommitHalt = VL_RANDOM_I(1);
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top->fpuRspHalt = VL_RANDOM_I(1);
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#endif
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@ -3815,10 +3820,10 @@ string riscvTestMemory[] = {
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string riscvTestFloat[] = {
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"rv32uf-p-fmadd",
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"rv32uf-p-fadd",
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"rv32uf-p-fcmp",
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"rv32uf-p-fcvt_w",
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"rv32uf-p-fmadd",
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"rv32uf-p-ldst",
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"rv32uf-p-recoding",
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"rv32uf-p-fclass",
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@ -3830,9 +3835,9 @@ string riscvTestFloat[] = {
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string riscvTestDouble[] = {
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"rv32ud-p-fmadd",
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"rv32ud-p-fadd",
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"rv32ud-p-fcvt",
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"rv32ud-p-fmadd",
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"rv32ud-p-recoding",
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"rv32ud-p-fclass",
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"rv32ud-p-fcvt_w",
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