Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix MPP to only retain legal values

This commit is contained in:
Dolu1990 2022-05-24 11:14:34 +02:00
parent 209fc719e8
commit 4c4913c703
1 changed files with 10 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
src/main/scala/vexriscv/plugin/CsrPlugin.scala
View File

@ -713,11 +713,20 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
misaAccess(CSR.MISA, xlen-2 -> misa.base , 0 -> misa.extensions)
//Machine CSR
READ_WRITE(CSR.MSTATUS,11 -> mstatus.MPP, 7 -> mstatus.MPIE, 3 -> mstatus.MIE)
READ_WRITE(CSR.MSTATUS, 7 -> mstatus.MPIE, 3 -> mstatus.MIE)
READ_ONLY(CSR.MIP, 11 -> mip.MEIP, 7 -> mip.MTIP)
READ_WRITE(CSR.MIP, 3 -> mip.MSIP)
READ_WRITE(CSR.MIE, 11 -> mie.MEIE, 7 -> mie.MTIE, 3 -> mie.MSIE)
r(CSR.MSTATUS, 11 -> mstatus.MPP)
onWrite(CSR.MSTATUS){
switch(writeData()(12 downto 11)){
is(3){ mstatus.MPP := 3 }
if(supervisorGen) is(1){ mstatus.MPP := 1 }
if(userGen) is(0){ mstatus.MPP := 0 }
}
}
mtvecAccess(CSR.MTVEC, 2 -> mtvec.base, 0 -> mtvec.mode)
mepcAccess(CSR.MEPC, mepc)
if(mscratchGen) READ_WRITE(CSR.MSCRATCH, mscratch)