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add retiming to the dataCache waysHit 

Add exception catches in the default briey configuration
This commit is contained in:
Charles Papon 2017-06-26 14:02:25 +02:00
parent e9e7cf9e7a
commit 4d7455f9c3
2 changed files with 14 additions and 11 deletions
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18
src/main/scala/VexRiscv/demo/Briey.scala
View File

@ -197,9 +197,9 @@ class Briey(config: BrieyConfig) extends Component{
addressWidth = 32,
cpuDataWidth = 32,
memDataWidth = 32,
catchIllegalAccess = false,
catchAccessFault = false,
catchMemoryTranslationMiss = false,
catchIllegalAccess = true,
catchAccessFault = true,
catchMemoryTranslationMiss = true,
asyncTagMemory = false,
twoStageLogic = true
)
@ -220,10 +220,10 @@ class Briey(config: BrieyConfig) extends Component{
addressWidth = 32,
cpuDataWidth = 32,
memDataWidth = 32,
catchAccessError = false,
catchIllegal = false,
catchUnaligned = false,
catchMemoryTranslationMiss = false
catchAccessError = true,
catchIllegal = true,
catchUnaligned = true,
catchMemoryTranslationMiss = true
),
memoryTranslatorPortConfig = null
// memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
@ -234,7 +234,7 @@ class Briey(config: BrieyConfig) extends Component{
ioRange = _(31 downto 28) === 0xF
),
new DecoderSimplePlugin(
catchIllegalInstruction = false
catchIllegalInstruction = true
),
new RegFilePlugin(
regFileReadyKind = Plugin.SYNC,
@ -259,7 +259,7 @@ class Briey(config: BrieyConfig) extends Component{
new DebugPlugin(axiClockDomain),
new BranchPlugin(
earlyBranch = false,
catchAddressMisaligned = false,
catchAddressMisaligned = true,
prediction = STATIC
),
new CsrPlugin(

7
src/main/scala/VexRiscv/ip/DataCache.scala
View File

@ -17,6 +17,7 @@ case class DataCacheConfig( cacheSize : Int,
catchUnaligned : Boolean,
catchMemoryTranslationMiss : Boolean,
clearTagsAfterReset : Boolean = true,
waysHitRetime : Boolean = true,
tagSizeShift : Int = 0){ //Used to force infering ram
def burstSize = bytePerLine*8/memDataWidth
val burstLength = bytePerLine/(memDataWidth/8)
@ -478,8 +479,10 @@ class DataCache(p : DataCacheConfig) extends Component{
val stageB = new Area {
val request = RegNextWhen(stageA.request, !io.cpu.writeBack.isStuck)
val mmuRsp = RegNextWhen(io.cpu.memory.mmuBus.rsp, !io.cpu.writeBack.isStuck)
// val waysHit = RegNextWhen(way.tagReadRspTwoRegIn.used && stageA.mmuRsp.physicalAddress(tagRange) === way.tagReadRspTwoRegIn.address,!io.cpu.writeBack.isStuck) //Manual retiming
val waysHit = way.tagReadRspTwo.used && mmuRsp.physicalAddress(tagRange) === way.tagReadRspTwo.address
val waysHit = if(waysHitRetime)
RegNextWhen(way.tagReadRspTwoRegIn.used && io.cpu.memory.mmuBus.rsp.physicalAddress(tagRange) === way.tagReadRspTwoRegIn.address,!io.cpu.writeBack.isStuck) //Manual retiming
else
way.tagReadRspTwo.used && mmuRsp.physicalAddress(tagRange) === way.tagReadRspTwo.address
//Loader interface