DataCache split redo / refilling execute stage halt

src/main/scala/vexriscv/ip/DataCache.scala

@@ -110,10 +110,11 @@ case class DataCacheCpuExecute(p : DataCacheConfig) extends Bundle with IMasterS
   val address = UInt(p.addressWidth bit)
   val haltIt = Bool
   val args = DataCacheCpuExecuteArgs(p)
+  val refilling = Bool
 
   override def asMaster(): Unit = {
     out(isValid, args, address)
-    in(haltIt)
+    in(haltIt, refilling)
   }
 }
 
@@ -1072,7 +1073,9 @@ class DataCache(val p : DataCacheConfig, mmuParameter : MemoryTranslatorBusParam
       waysAllocator := (waysAllocator ## waysAllocator.msb).resized
     }
 
-    io.cpu.redo setWhen(valid)
+    io.cpu.redo setWhen(valid.rise())
+    io.cpu.execute.refilling := valid
+
     stageB.mmuRspFreeze setWhen(stageB.loaderValid || valid)
   }
 

src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala

@@ -275,8 +275,8 @@ class DBusCachedPlugin(val config : DataCacheConfig,
 
       insert(MEMORY_ADDRESS_LOW) := cache.io.cpu.execute.address(1 downto 0)
 
-      when(cache.io.cpu.redo && arbitration.isValid && input(MEMORY_ENABLE)){
-        arbitration.haltItself := True
+      when(cache.io.cpu.execute.refilling && arbitration.isValid){
+        arbitration.haltByOther := True
       }
 
       if(relaxedMemoryTranslationRegister) {
@@ -400,7 +400,7 @@ class DBusCachedPlugin(val config : DataCacheConfig,
         decode.arbitration.haltByOther := True
         val exceptionService = pipeline.service(classOf[ExceptionService])
         when(!stagesFromExecute.map(s => s.arbitration.isValid || exceptionService.isExceptionPending(s)).orR){
-          when(!cache.io.cpu.redo) {
+          when(!cache.io.cpu.execute.refilling) {
             cache.io.cpu.execute.isValid := True
             dBusAccess.cmd.ready := !execute.arbitration.isStuck
           }