Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

IBusSimplePlugin AHB bridge fix, pass tests

This commit is contained in:
Dolu1990 2019-03-28 10:12:42 +01:00
parent b0522cb491
commit 53c05c31c7
3 changed files with 12 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
View File

@ -211,7 +211,7 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{
bus.HSIZE := B(this.cmd.size, 3 bits) bus.HSIZE := B(this.cmd.size, 3 bits)
bus.HBURST := 0 bus.HBURST := 0
bus.HPROT := "1111" bus.HPROT := "1111"
bus.HTRANS := B"0" ## this.cmd.valid bus.HTRANS := this.cmd.valid ## B"0"
bus.HMASTLOCK := False bus.HMASTLOCK := False
bus.HWDATA := RegNextWhen(this.cmd.data, bus.HREADY) bus.HWDATA := RegNextWhen(this.cmd.data, bus.HREADY)
this.cmd.ready := bus.HREADY this.cmd.ready := bus.HREADY

2
src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
View File

@ -162,7 +162,7 @@ case class IBusSimpleBus(interfaceKeepData : Boolean = false) extends Bundle wit
bus.HSIZE := 2 bus.HSIZE := 2
bus.HBURST := 0 bus.HBURST := 0
bus.HPROT := "1110" bus.HPROT := "1110"
bus.HTRANS := B"0" ## this.cmd.valid bus.HTRANS := this.cmd.valid ## B"0"
bus.HMASTLOCK := False bus.HMASTLOCK := False
bus.HWDATA.assignDontCare() bus.HWDATA.assignDontCare()
this.cmd.ready := bus.HREADY this.cmd.ready := bus.HREADY

18
src/test/cpp/regression/main.cpp
View File

@ -972,7 +972,7 @@ public:
if(bootPc != -1) top->VexRiscv->core->prefetch_pc = bootPc; if(bootPc != -1) top->VexRiscv->core->prefetch_pc = bootPc;
#else #else
if(bootPc != -1) { if(bootPc != -1) {
#if defined(IBUS_SIMPLE) || defined(IBUS_SIMPLE_WISHBONE) #if defined(IBUS_SIMPLE) || defined(IBUS_SIMPLE_WISHBONE) || defined(IBUS_SIMPLE_AHBLITE3)
top->VexRiscv->IBusSimplePlugin_fetchPc_pcReg = bootPc; top->VexRiscv->IBusSimplePlugin_fetchPc_pcReg = bootPc;
#ifdef COMPRESSED #ifdef COMPRESSED
top->VexRiscv->IBusSimplePlugin_decodePc_pcReg = bootPc; top->VexRiscv->IBusSimplePlugin_decodePc_pcReg = bootPc;
@ -1287,7 +1287,8 @@ public:
VVexRiscv* top; VVexRiscv* top;
uint32_t iBusAhbLite3_HRDATA; uint32_t iBusAhbLite3_HRDATA;
bool iBusAhbLite3_HRESP, iBusAhbLite3_HREADY; bool iBusAhbLite3_HRESP;
bool pending;
IBusSimpleAhbLite3(Workspace* ws){ IBusSimpleAhbLite3(Workspace* ws){
this->ws = ws; this->ws = ws;
@ -1295,6 +1296,7 @@ public:
} }
virtual void onReset(){ virtual void onReset(){
pending = false;
top->iBusAhbLite3_HREADY = 1; top->iBusAhbLite3_HREADY = 1;
top->iBusAhbLite3_HRESP = 0; top->iBusAhbLite3_HRESP = 0;
} }
@ -1302,22 +1304,22 @@ public:
virtual void preCycle(){ virtual void preCycle(){
if (top->iBusAhbLite3_HTRANS == 2 && top->iBusAhbLite3_HREADY && !top->iBusAhbLite3_HWRITE) { if (top->iBusAhbLite3_HTRANS == 2 && top->iBusAhbLite3_HREADY && !top->iBusAhbLite3_HWRITE) {
ws->iBusAccess(top->iBusAhbLite3_HADDR,&iBusAhbLite3_HRDATA,&iBusAhbLite3_HRESP); ws->iBusAccess(top->iBusAhbLite3_HADDR,&iBusAhbLite3_HRDATA,&iBusAhbLite3_HRESP);
pending = true;
} }
} }
virtual void postCycle(){ virtual void postCycle(){
if(top->iBusAhbLite3_HREADY && (!ws->iStall || VL_RANDOM_I(7) < 100)){ if(ws->iStall)
IBusSimpleAvalonRsp rsp = rsps.front(); rsps.pop(); top->iBusAhbLite3_HREADY = (!ws->iStall || VL_RANDOM_I(7) < 100);
if(pending && top->iBusAhbLite3_HREADY){
top->iBusAhbLite3_HRDATA = iBusAhbLite3_HRDATA; top->iBusAhbLite3_HRDATA = iBusAhbLite3_HRDATA;
top->iBusAhbLite3_HREADY = iBusAhbLite3_HREADY;
top->iBusAhbLite3_HRESP = iBusAhbLite3_HRESP; top->iBusAhbLite3_HRESP = iBusAhbLite3_HRESP;
pending = false;
} else { } else {
top->iBusAhbLite3_HRESP = 0;
top->iBusAhbLite3_HRDATA = VL_RANDOM_I(32); top->iBusAhbLite3_HRDATA = VL_RANDOM_I(32);
top->iBusAhbLite3_HRESP = VL_RANDOM_I(1); top->iBusAhbLite3_HRESP = VL_RANDOM_I(1);
} }
if(ws->iStall)
top->iBusAhbLite3_HREADY = VL_RANDOM_I(7) < 100;
} }
}; };
#endif #endif