Add SIMD_ADD regression and config (show case)
This commit is contained in:
Charles Papon
parent
3307d6c3b5
commit
54b06e6438
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@ -40,4 +40,5 @@ obj_dir
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*.memTrace
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*.regTrace
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*.tcl
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*.o
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@ -0,0 +1,59 @@
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package vexriscv.demo
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import spinal.core._
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import vexriscv.plugin._
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import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
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/**
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* Created by spinalvm on 15.06.17.
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*/
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object GenCustomSimdAdd extends App{
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def cpu() = new VexRiscv(
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config = VexRiscvConfig(
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plugins = List(
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new SimdAddPlugin,
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new PcManagerSimplePlugin(
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resetVector = 0x00000000l,
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relaxedPcCalculation = false
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),
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new IBusSimplePlugin(
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interfaceKeepData = false,
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catchAccessFault = false
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),
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new DBusSimplePlugin(
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catchAddressMisaligned = false,
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catchAccessFault = false
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),
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new DecoderSimplePlugin(
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catchIllegalInstruction = false
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),
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new RegFilePlugin(
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regFileReadyKind = plugin.SYNC,
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zeroBoot = true
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),
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new IntAluPlugin,
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new SrcPlugin(
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separatedAddSub = false,
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executeInsertion = false
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),
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new LightShifterPlugin,
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new HazardSimplePlugin(
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bypassExecute = false,
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bypassMemory = false,
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bypassWriteBack = false,
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bypassWriteBackBuffer = false,
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pessimisticUseSrc = false,
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pessimisticWriteRegFile = false,
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pessimisticAddressMatch = false
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),
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new BranchPlugin(
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earlyBranch = false,
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catchAddressMisaligned = false,
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prediction = NONE
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),
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new YamlPlugin("cpu0.yaml")
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)
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)
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)
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SpinalVerilog(cpu())
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}
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@ -0,0 +1,63 @@
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build/custom_simd_add.elf: file format elf32-littleriscv
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Disassembly of section .crt_section:
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00000000 <_start>:
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0: 00100e13 li t3,1
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4: 060000b3 0x60000b3
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8: 08009c63 bnez ra,a0 <fail>
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c: 00200e13 li t3,2
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10: 00000093 li ra,0
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14: 00000113 li sp,0
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18: 062080b3 0x62080b3
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1c: 08009263 bnez ra,a0 <fail>
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20: 00300e13 li t3,3
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24: 010200b7 lui ra,0x1020
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28: 30408093 addi ra,ra,772 # 1020304 <pass+0x1020258>
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2c: 00000113 li sp,0
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30: 062081b3 0x62081b3
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34: 06119663 bne gp,ra,a0 <fail>
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38: 00400e13 li t3,4
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3c: 03061237 lui tp,0x3061
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40: 90c20213 addi tp,tp,-1780 # 306090c <pass+0x3060860>
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44: 010200b7 lui ra,0x1020
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48: 30408093 addi ra,ra,772 # 1020304 <pass+0x1020258>
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4c: 02040137 lui sp,0x2040
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50: 60810113 addi sp,sp,1544 # 2040608 <pass+0x204055c>
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54: 062081b3 0x62081b3
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58: 04419463 bne gp,tp,a0 <fail>
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5c: 00500e13 li t3,5
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60: ff000237 lui tp,0xff000
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64: 10220213 addi tp,tp,258 # ff000102 <pass+0xff000056>
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68: fff00093 li ra,-1
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6c: 00010137 lui sp,0x10
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70: 20310113 addi sp,sp,515 # 10203 <pass+0x10157>
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74: 062081b3 0x62081b3
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78: 02419463 bne gp,tp,a0 <fail>
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7c: 00600e13 li t3,6
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80: 00600293 li t0,6
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84: 00100093 li ra,1
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88: 00200113 li sp,2
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8c: 00300193 li gp,3
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90: 062080b3 0x62080b3
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94: 063080b3 0x63080b3
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98: 00509463 bne ra,t0,a0 <fail>
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9c: 0100006f j ac <pass>
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000000a0 <fail>:
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a0: f0100137 lui sp,0xf0100
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a4: f2410113 addi sp,sp,-220 # f00fff24 <pass+0xf00ffe78>
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a8: 01c12023 sw t3,0(sp)
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000000ac <pass>:
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ac: f0100137 lui sp,0xf0100
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b0: f2010113 addi sp,sp,-224 # f00fff20 <pass+0xf00ffe74>
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b4: 00012023 sw zero,0(sp)
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b8: 00000013 nop
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bc: 00000013 nop
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c0: 00000013 nop
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c4: 00000013 nop
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c8: 00000013 nop
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cc: 00000013 nop
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Binary file not shown.
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@ -0,0 +1,14 @@
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:10000000130E1000B3000006639C0008130E2000BE
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:100010009300000013010000B380200663920008E3
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:10002000130E3000B700020193804030130100002E
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:10003000B381200663961106130E400037120603A3
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:100040001302C290B70002019380403037010402CE
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:1000500013018160B381200663944104130E5000A4
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:10006000370200FF130222109300F0FF3701010056
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:1000700013013120B381200663944102130E600006
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:1000800093026000930010001301200093013000E0
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:10009000B3802006B3803006639450006F000001E7
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:1000A000370110F0130141F22320C101370110F094
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:1000B000130101F2232001001300000013000000CF
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:1000C00013000000130000001300000013000000E4
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:00000001FF
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@ -0,0 +1,30 @@
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Memory Configuration
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Name Origin Length Attributes
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onChipRam 0x0000000000000000 0x0000000000002000 w !xr
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*default* 0x0000000000000000 0xffffffffffffffff
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Linker script and memory map
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LOAD build/src/crt.o
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LOAD /opt/rv32i/bin/../lib/gcc/riscv32-unknown-elf/7.1.1/libgcc.a
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START GROUP
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LOAD /opt/rv32i/bin/../lib/gcc/riscv32-unknown-elf/7.1.1/../../../../riscv32-unknown-elf/lib/libc.a
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LOAD /opt/rv32i/bin/../lib/gcc/riscv32-unknown-elf/7.1.1/../../../../riscv32-unknown-elf/lib/libgloss.a
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END GROUP
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LOAD /opt/rv32i/bin/../lib/gcc/riscv32-unknown-elf/7.1.1/libgcc.a
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0x0000000000000000 . = 0x0
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.crt_section 0x0000000000000000 0xd0
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0x0000000000000000 . = ALIGN (0x4)
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*crt.o(.text)
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.text 0x0000000000000000 0xd0 build/src/crt.o
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0x0000000000000000 _start
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OUTPUT(build/custom_simd_add.elf elf32-littleriscv)
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.data 0x00000000000000d0 0x0
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.data 0x00000000000000d0 0x0 build/src/crt.o
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.bss 0x00000000000000d0 0x0
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.bss 0x00000000000000d0 0x0 build/src/crt.o
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@ -0,0 +1,14 @@
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@00000000
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13 0E 10 00 B3 00 00 06 63 9C 00 08 13 0E 20 00
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93 00 00 00 13 01 00 00 B3 80 20 06 63 92 00 08
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13 0E 30 00 B7 00 02 01 93 80 40 30 13 01 00 00
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B3 81 20 06 63 96 11 06 13 0E 40 00 37 12 06 03
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13 02 C2 90 B7 00 02 01 93 80 40 30 37 01 04 02
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13 01 81 60 B3 81 20 06 63 94 41 04 13 0E 50 00
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37 02 00 FF 13 02 22 10 93 00 F0 FF 37 01 01 00
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13 01 31 20 B3 81 20 06 63 94 41 02 13 0E 60 00
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93 02 60 00 93 00 10 00 13 01 20 00 93 01 30 00
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B3 80 20 06 B3 80 30 06 63 94 50 00 6F 00 00 01
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37 01 10 F0 13 01 41 F2 23 20 C1 01 37 01 10 F0
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13 01 01 F2 23 20 01 00 13 00 00 00 13 00 00 00
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13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00
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@ -0,0 +1,73 @@
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PROJ_NAME=custom_simd_add
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RISCV_PATH=/opt/rv32i/
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CFLAGS += -march=rv32i -mabi=ilp32
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RISCV_NAME = riscv32-unknown-elf
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RISCV_OBJCOPY = $(RISCV_PATH)/bin/$(RISCV_NAME)-objcopy
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RISCV_OBJDUMP = $(RISCV_PATH)/bin/$(RISCV_NAME)-objdump
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RISCV_CLIB=$(RISCV_PATH)$(RISCV_NAME)/lib/
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RISCV_CC=$(RISCV_PATH)/bin/$(RISCV_NAME)-gcc
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LDSCRIPT=src/ld
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SRCS = $(wildcard src/*.c) \
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$(wildcard src/*.cpp) \
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$(wildcard src/*.S)
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CFLAGS += -static
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LDFLAGS += -e_start -T $(LDSCRIPT) -nostartfiles -Wl,-Map,$(OBJDIR)/$(PROJ_NAME).map -Wl,--print-memory-usage
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OBJDIR = build
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OBJS := $(SRCS)
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OBJS := $(OBJS:.c=.o)
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OBJS := $(OBJS:.cpp=.o)
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OBJS := $(OBJS:.S=.o)
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OBJS := $(addprefix $(OBJDIR)/,$(OBJS))
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all: $(OBJDIR)/$(PROJ_NAME).elf $(OBJDIR)/$(PROJ_NAME).hex $(OBJDIR)/$(PROJ_NAME).asm $(OBJDIR)/$(PROJ_NAME).v
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@echo "done"
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$(OBJDIR)/%.elf: $(OBJS) | $(OBJDIR)
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$(RISCV_CC) $(CFLAGS) -o $@ $^ $(LDFLAGS) $(LIBS)
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%.hex: %.elf
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$(RISCV_OBJCOPY) -O ihex $^ $@
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%.bin: %.elf
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$(RISCV_OBJCOPY) -O binary $^ $@
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%.v: %.elf
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$(RISCV_OBJCOPY) -O verilog $^ $@
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%.asm: %.elf
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$(RISCV_OBJDUMP) -S -d $^ > $@
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$(OBJDIR)/%.o: %.c
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mkdir -p $(dir $@)
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$(RISCV_CC) -c $(CFLAGS) $(INC) -o $@ $^
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$(OBJDIR)/%.o: %.cpp
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mkdir -p $(dir $@)
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$(RISCV_CC) -c $(CFLAGS) $(INC) -o $@ $^
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$(OBJDIR)/%.o: %.S
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mkdir -p $(dir $@)
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$(RISCV_CC) -c $(CFLAGS) -o $@ $^ -D__ASSEMBLY__=1
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$(OBJDIR):
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mkdir -p $@
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clean:
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rm -f $(OBJDIR)/$(PROJ_NAME).elf
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rm -f $(OBJDIR)/$(PROJ_NAME).hex
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rm -f $(OBJDIR)/$(PROJ_NAME).map
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rm -f $(OBJDIR)/$(PROJ_NAME).v
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rm -f $(OBJDIR)/$(PROJ_NAME).asm
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find $(OBJDIR) -type f -name '*.o' -print0 | xargs -0 -r rm
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.SECONDARY: $(OBJS)
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@ -0,0 +1,72 @@
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.globl _start
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_start:
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#define r_type_insn(_f7, _rs2, _rs1, _f3, _rd, _opc) \
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.word (((_f7) << 25) | ((_rs2) << 20) | ((_rs1) << 15) | ((_f3) << 12) | ((_rd) << 7) | ((_opc) << 0))
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#define SIMD_ADD(_rd, _rs1, _rs2 ) \
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r_type_insn(0b0000011, _rs2, _rs1, 0b000, _rd, 0b0110011)
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//Test 1
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li x28, 1
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SIMD_ADD(1, 0, 0)
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bne x1, x0, fail
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//Test 2
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li x28, 2
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li x1, 0x00000000
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li x2, 0x00000000
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SIMD_ADD(1, 1, 2)
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bne x1, x0, fail
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//Test 3
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li x28, 3
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li x1, 0x01020304
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li x2, 0x00000000
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SIMD_ADD(3, 1, 2)
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bne x3, x1, fail
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//Test 4
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li x28, 4
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li x4, 0x0306090C
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li x1, 0x01020304
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li x2, 0x02040608
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SIMD_ADD(3, 1, 2)
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bne x3, x4, fail
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//Test 5
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li x28, 5
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li x4, 0xFF000102
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li x1, 0xFFFFFFFF
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li x2, 0x00010203
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SIMD_ADD(3, 1, 2)
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bne x3, x4, fail
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//Test 5
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li x28, 6
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li x5, 0x00000006
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li x1, 0x00000001
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li x2, 0x00000002
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li x3, 0x00000003
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SIMD_ADD(1, 1, 2)
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SIMD_ADD(1, 1, 3)
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bne x1, x5, fail
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j pass
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fail: //x28 => error code
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li x2, 0xF00FFF24
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sw x28, 0(x2)
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pass:
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li x2, 0xF00FFF20
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sw x0, 0(x2)
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nop
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nop
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nop
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nop
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nop
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nop
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@ -0,0 +1,17 @@
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OUTPUT_ARCH( "riscv" )
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MEMORY {
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onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x00000000, LENGTH = 8K
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}
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SECTIONS
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{
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. = 0x000;
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.crt_section :
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{
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. = ALIGN(4);
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*crt.o(.text)
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} > onChipRam
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}
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@ -79,6 +79,9 @@ uint32_t hToI(char *c, uint32_t size) {
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void loadHexImpl(string path,Memory* mem) {
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FILE *fp = fopen(&path[0], "r");
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if(fp == 0){
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cout << path << " not found" << endl;
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}
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fseek(fp, 0, SEEK_END);
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uint32_t size = ftell(fp);
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fseek(fp, 0, SEEK_SET);
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@ -275,6 +278,10 @@ public:
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else
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fail();
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break;
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case 0xF00FFF24u:
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cout << "TEST ERROR CODE " << *data << endl;
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fail();
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break;
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#endif
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case 0xF00FFF48u: mTimeCmp = (mTimeCmp & 0xFFFFFFFF00000000) | *data;break;
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case 0xF00FFF4Cu: mTimeCmp = (mTimeCmp & 0x00000000FFFFFFFF) | (((uint64_t)*data) << 32); /*cout << "mTimeCmp <= " << mTimeCmp << endl; */break;
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@ -1711,6 +1718,11 @@ int main(int argc, char **argv, char **env) {
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redo(REDO,DebugPluginTest().run(1e6););
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#endif
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#endif
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#ifdef CUSTOM_SIMD_ADD
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redo(REDO,Workspace("custom_simd_add").loadHex("../custom/simd_add/build/custom_simd_add.hex")->bootAt(0x00000000u)->run(50e3););
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#endif
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#ifdef DHRYSTONE
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Dhrystone("dhrystoneO3_Stall","dhrystoneO3",true,true).run(1.1e6);
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#if defined(MUL) && defined(DIV)
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@ -10,6 +10,7 @@ CSR?=yes
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MMU?=yes
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DEBUG_PLUGIN?=STD
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DEBUG_PLUGIN_EXTERNAL?=no
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CUSTOM_SIMD_ADD?=no
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DHRYSTONE=yes
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FREERTOS=no
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REDO?=10
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@ -37,6 +38,10 @@ ifeq ($(CSR),yes)
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ADDCFLAGS += -CFLAGS -DCSR
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endif
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ifeq ($(CUSTOM_SIMD_ADD),yes)
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ADDCFLAGS += -CFLAGS -DCUSTOM_SIMD_ADD
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endif
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ifeq ($(TRACE_WITH_TIME),yes)
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ADDCFLAGS += -CFLAGS -DTRACE_WITH_TIME
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endif
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